Patents by Inventor Michael P. Chudzik
Michael P. Chudzik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7772016Abstract: Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.Type: GrantFiled: April 4, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Russell D. Allen, Stephen L. Brown, Alessandro C. Callegari, Michael P. Chudzik, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20100187610Abstract: A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Unoh Kwon, Siddarth A. Krishnan, Takashi Ando, Michael P. Chudzik, Martin M. Frank, William K. Henson, Rashmi Jha, Yue Liang, Vijay Narayanan, Ravikumar Ramachandran, Keith Kwong Hon Wong
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Publication number: 20100187643Abstract: A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL P. CHUDZIK, MICHAEL A. GRIBELYUK, RASHMI JHA, RENEE T. MO, NAIM MOUMEN, KEITH KWONG HON WONG
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Publication number: 20100181630Abstract: A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Ricardo A. Donaton, Naim Moumen, Hongwen Yan
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Patent number: 7754594Abstract: A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.Type: GrantFiled: January 26, 2009Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Michael P Chudzik, Michael A Gribelyuk, Rashmi Jha, Renee T Mo, Naim Moumen, Keith Kwong Hon Wong
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Patent number: 7750418Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures.Type: GrantFiled: May 22, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri, Yun Y. Wang, Keith Kwong Hon Wong
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Patent number: 7741188Abstract: A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.Type: GrantFiled: March 24, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Eduard A. Cartier, Michael P. Chudzik, Naim Moumen
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Patent number: 7732872Abstract: A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.Type: GrantFiled: October 25, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Michael P. Chudzik, Ramachandra Divakaruni, Geng Wang, Robert C. Wong, Haining S. Yang
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Publication number: 20100044805Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.Type: ApplicationFiled: October 30, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Renee T. Mo, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri, Sufi Zafar
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Publication number: 20100041221Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: August 14, 2009Publication date: February 18, 2010Applicant: International Business Machines CoporationInventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20100038725Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
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Publication number: 20090308636Abstract: Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.Type: ApplicationFiled: June 12, 2008Publication date: December 17, 2009Applicant: International Business Machines CorporationInventors: Michael P Chudzik, Troy Graves-Abe, Rashmi Jha, Renee T. Mo, Keith Kwong Hon Wong
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Publication number: 20090294920Abstract: Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Michael P. Chudzik, Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong, Ying H. Tsang
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Patent number: 7622341Abstract: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.Type: GrantFiled: January 16, 2008Date of Patent: November 24, 2009Assignees: International Business Machines Corporation, Advanced Micro Device, Inc.Inventors: Michael P. Chudzik, Dominic J. Schepis, Linda Black
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Publication number: 20090283838Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
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Publication number: 20090283830Abstract: A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.Type: ApplicationFiled: July 23, 2009Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20090280631Abstract: The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.Type: ApplicationFiled: May 9, 2008Publication date: November 12, 2009Inventors: Jeffrey P. Gambino, Michael P. Chudzik, Renee T. Mo
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Patent number: 7611979Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.Type: GrantFiled: February 12, 2007Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Renee T. Mo, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri, Sufi Zafar
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Publication number: 20090250760Abstract: Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET region using a mask; forming a forming a second high-k dielectric layer and a second metal layer over the substrate, the first high-k dielectric layer being different then the second high-k dielectric layer and the first metal being different than the second metal; removing the second high-k dielectric layer and the second metal over the PFET region using a mask; depositing a polysilicon over the substrate; and forming a gate over the NFET region and the PFET region by simultaneously etching the polysilicon, the first high-k dielectric layer, the first metal, the second high-k dielectric layer and the second metal.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, William K. Henson, Naim Moumen, Dae-Gyu Park, Hongwen Yan
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Publication number: 20090236691Abstract: A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas W. Dyer, Eduard A. Cartier, Michael P. Chudzik, Naim Moumen