Abstract: Methods and apparatus are provided for a shield to protect a surface from the impact of hyper-velocity projectiles. The apparatus comprises a foam material that is configured to cover the surface to be protected and is attached directly to that surface. A coating material is typically disposed on the outer surface of the foam material and may penetrate the foam material to a predetermined depth. The foam material and the coating material are selected to form a composite having predetermined values of sonic velocity, toughness, and thermal conductivity. The composite of foam material and coating material can be significantly lighter in weight than a metal shield having equivalent protective characteristics.

Abstract: Methods and apparatus are provided for a lightweight heat rejection system suitable for spacecraft applications. The apparatus comprises a manifold configured with an array of heat pipes in thermal contact with a manifold coolant. The heat pipes transfer the coolant heat to associated bumper/radiators external to the manifold. The bumper/radiators are fabricated from a lightweight thermally conductive foam material. The bumper portion protects the heat pipe from space debris and the radiator portion dissipates the heat transferred from the heat pipe through the bumper to the radiator portion. The foam bumper/radiator can be cast over the heat pipe in a relatively simple and economical manufacturing process.

Abstract: A combustor for a gas powered turbine which employs a heat exchanger and a catalyst to combust a fuel without the emission of undesired chemical species. A gas powered turbine requires expanding gases to power the turbine blades. Fuel is combusted to produce the required gases. A catalyst is employed to lower the combustion temperature of the fuel. The catalyst is placed on a set of tubes in the heat exchanger such that a portion of the thermal energy may be transferred to the air before it engages the catalyst. After encountering the catalyst, the combusted fuel increases the temperature of the air to an auto-ignition temperature so that no other ignition source is needed to combust additional fuel.

Abstract: A digital television/local bus interface logic supports handling of digital television (DTV) data with non-tearing. The interface logic provides a dual frame buffer DTV architecture in which a pair of DTV/local bus frame buffers alternate functions: one frame buffer stores incoming DTV data and the other frame buffer stores the outgoing DTV data. When a refresh of a display device reaches a programmed position of the display device, the interface logic determines which frame buffer is being updated by the incoming DTV data. The outgoing DTV data is then read from an opposite frame buffer and transmitted to the display device. The interface logic receives a horizontal sync signal and a vertical sync signal from the graphics controller for monitoring refresh of the display device. The interface logic also provides an architecture for transferring decoded DTV data over a local bus to the graphics controller.

Abstract: Systems and methods capable of producing electrical power from solar energy through the use of air cycles without fossil fuel combustion. The system includes a solar receiver, a generator, a compressor, and an expander. The expander is coupled to the generator to drive the generator and coupled to the compressor to drive the compressor. The system uses solar generated heat from the solar receiver to heat compressed air from the compressor. The solar generated heat can be directly transferred from the solar receiver to the compressed air as the compressed air flows through receiver tubes of the solar receiver, or the solar receiver can transfer the solar generated heat to a liquid metal, with the liquid metal transferring thermal energy to the compressed air. The expander receives and expands the heated compressed air to drive the generator to produce electricity, and to drive the compressor to compress air.

Abstract: Method and apparatuses are provided for removing thermal energy from a nuclear reactor, which are fault tolerant. The apparatus includes at least one heat pipe configured to absorb thermal energy produced by the nuclear reactor. In addition, the apparatus includes a first compartment thermally coupled to the at least one heat pipe. The first compartment is configured to contain a first gas. Furthermore, the apparatus includes a second compartment thermally coupled to the at least one heat pipe. The second compartment is configured to contain a second gas and configured to isolate the second gas from the first gas.

Abstract: Systems and methods capable of producing electrical power from solar energy through the use of air cycles without fossil fuel combustion. The system includes a solar receiver, a generator, a compressor, and an expander. The expander is coupled to the generator to drive the generator and coupled to the compressor to drive the compressor. The system uses solar generated heat from the solar receiver to heat compressed air from the compressor. The solar generated heat can be directly transferred from the solar receiver to the compressed air as the compressed air flows through receiver tubes of the solar receiver, or the solar receiver can transfer the solar generated heat to a liquid metal, with the liquid metal transferring thermal energy to the compressed air. The expander receives and expands the heated compressed air to drive the generator to produce electricity, and to drive the compressor to compress air.

Abstract: Methods and apparatuses are provided for removing thermal energy from a nuclear reactor, which are fault tolerant. The apparatus includes at least one heat pipe configured to absorb thermal energy produced by the nuclear reactor. In addition, the apparatus includes a first compartment thermally coupled to the at least one heat pipe. The first compartment is configured to contain a first gas. Furthermore, the apparatus includes a second compartment thermally coupled to the at least one heat pipe. The second compartment is configured to contain a second gas and configured to isolate the second gas from the first gas.

Abstract: A solar receiver system (10) has a solar receiver (12) that receives sun rays (14) directed thereto. The receiver (12) has a heat pipe (26) having working fluid (38) therein. The first end (28) of heat pipe (26) and a second end (30) form a respective first condenser (32) and a second condenser (34). An evaporator portion (36) is disposed between the ends (28,30). The first end (28) has an air manifold (42) therearound. The second end has a liquid manifold (48) therearound. The heated air from the air manifold (42) is provided to a power generation device (22). The power generation device (22) receives heated air from the air manifold (42) which is expanded in a turbine (68) to extract mechanical work therefrom. The turbine (68) may be coupled to a generator (78) for generating electrical power in response to the mechanical energy.

Abstract: In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

Abstract: A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell.

Abstract: In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

Abstract: A method and apparatus of allocating memory space in a main memory of a computer system to a unified memory architecture device. The main memory is associated with a physical address space. A required linear address range is determined for the video card, and the linear address range is mapped to scattered portions in the physical address space. A page table is created containing page frame numbers corresponding to page frames in the main memory, the page frames being allocated to the device. The page frames are non-contiguous blocks of the main memory. The device is associated with a linear address space. The frame numbers are loaded into a translation look-aside buffer (TLB) for converting a linear address in the linear address space to a physical address in the physical address space.

Abstract: In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

Abstract: A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.

Abstract: A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.

Abstract: An apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device, such as a bus bridge.

Abstract: A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.

Abstract: A multimedia system including a PCI bus master controller for transferring concurrent and independent video and audio data streams to video and audio devices. The controller includes a video request and DMA channel, a video sub-picture request and DMA channel, an audio request and DMA channel, and a decompressed video DMA and posted request channel for independently and concurrently transferring the data streams from host memory to the devices. The host processor builds lists of request packets in system memory and asynchronously submits the request packets to the controller. The request packets include commands which the request channels execute. The commands may include spinning on status conditions in registers of the multimedia devices, writing to registers of the devices, or performing bus master transfers of multimedia data streams from system memory to the devices. The device register accesses are performed by the controller on local buses thereby reducing PCI bus traffic.

Abstract: A method and apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device.