Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A method of manufacturing a micro-passage heat exchanger includes preparing a substrate of multiple square tubes, configuring multiple layers of the square tubes in a vertical plane, interposing between each layer a braze alloy to form a core, bonding the multiple layers of multiple tubes to form a core mass, forming in alternate tube layers counter flow fluid channels, providing the core mass with sides and manifolds, and brazing the heat exchanger.

Abstract: A combined solar concentrator and radiator assembly (10) is provided in a relatively lightweight and compact geometry adapted particularly for use in electrical power generation systems in space. The solar concentrator - radiator assembly comprises a solar reflector of the Cassegrain type having primary and secondary reflelctor surfaces (14) and (26) for concentrating incident solar ration upon a thermal powered generator unit (16). The primary reflector surface (14) is formed on one side of an array of interleaved panels (30) adapted for movement between a compact stowed profile to fit within the cargo bay of a transport vehicle, and an extended deployed configuration. The reverse sides of these panels define a space radiator of extended surface area connected to the generator unit (16) by heat transfer members such as heat pipes (34) for purposes of dissipating excess heat to the surrounding space environment.

Abstract: A method and apparatus for combustion of a sulfur-containing fuel which substantially reduces the amount of gaseous sulfur compounds which would otherwise be emitted.A source of oxygen, a sulfur-containing fuel, and an inorganic alkaline absorbent are reacted under controlled conditions of temperature, stoichiometry, and residence time whereby the inorganic alkaline absorbent reacts with the fuel sulfur to form a mixture of combustion products and desired solid sulfur compounds, the latter being readily removed utilizing conventional filtration equipment. In a preferred embodiment of the invention, the mixture of fuel and combustion products is passed into a nitrogenous compound destruction zone wherein, under controlled conditions, the concentration of nitrogenous compounds present are reduced to a desired level.

Abstract: A method and apparatus for combustion of a sulfur-containing fuel which substantially reduces the amount of gaseous sulfur compounds which would otherwise be emitted.A source of oxygen, a sulfur-containing fuel, and an inorganic alkaline absorbent are reacted under controlled conditions of temperature, stoichiometry, and residence time whereby the inorganic alkaline absorbent reacts with the fuel sulfur to form a mixture of combustion products and desired solid sulfur compounds, the latter being readily removed utilizing conventional filtration equipment. In a preferred embodiment of the invention, the mixture of fuel and combustion products is passed into a nitrogenous compound destruction zone wherein, under controlled conditions, the concentration of nitrogenous compounds present are reduced to a desired level.