Patents by Inventor Michael P. Tenney
Michael P. Tenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9170273Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.Type: GrantFiled: December 9, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Terence L. Kane, Matthew F. Stanton, Michael P. Tenney
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Publication number: 20150160261Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.Type: ApplicationFiled: December 9, 2013Publication date: June 11, 2015Applicant: International Business Machines CorporationInventors: Terence L. Kane, Matthew F. Stanton, Michael P. Tenney
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Patent number: 9052338Abstract: An apparatus for electrical inspection is disclosed. The apparatus comprises an inert gas delivery system that delivers inert gas near a microscope imaging element and electrical test probes. A gas supply provides an inert gas such as argon or nitrogen. The inert gas displaces oxygen to prevent premature oxidation of the test probes. In one embodiment, one or more delivery tubes deliver inert gas to the measurement area.Type: GrantFiled: November 18, 2013Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Terence Lawrence Kane, Richard Walter Oldrey, Michael P. Tenney
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Publication number: 20140069165Abstract: An apparatus for electrical inspection is disclosed. The apparatus comprises an inert gas delivery system that delivers inert gas near a microscope imaging element and electrical test probes. A gas supply provides an inert gas such as argon or nitrogen. The inert gas displaces oxygen to prevent premature oxidation of the test probes. In one embodiment, one or more delivery tubes deliver inert gas to the measurement area.Type: ApplicationFiled: November 18, 2013Publication date: March 13, 2014Inventors: Terence Lawrence Kane, Richard Walter Oldrey, Michael P. Tenney
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Patent number: 8368070Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8368069Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8367484Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8367483Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: January 27, 2012Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120126366Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120129340Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120126367Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20120122280Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: January 27, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 8125048Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: GrantFiled: October 7, 2009Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Patent number: 7993504Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: February 7, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Terence L. Kane, Darrell L. Miles, John D. Sylvestri, Michael P. Tenney
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Publication number: 20110079874Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.Type: ApplicationFiled: October 7, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Michael P. Tenney, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20080128086Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: ApplicationFiled: February 7, 2008Publication date: June 5, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Darrell L. Miles, John D. Sylvestri, Michael P. Tenney
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Patent number: 7371689Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: October 3, 2005Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Terence L Kane, Darrell L Miles, John D Sylvestri, Michael P Tenney
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Patent number: 7015146Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: January 6, 2004Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Terence L. Kane, Darrell L. Miles, John D. Sylyestri, Michael P. Tenney
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Patent number: 6888224Abstract: Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.Type: GrantFiled: June 30, 2003Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Terence Lawrence Kane, Michael P. Tenney
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Patent number: 6884641Abstract: This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.Type: GrantFiled: September 18, 2003Date of Patent: April 26, 2005Assignee: International Business Machines CorporationInventors: John Bruley, Terence Kane, Michael P. Tenney, Yun Yu Wang