Abstract: A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 ?m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 ?A with an aperture size less than 50 ?m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.

Abstract: A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 &mgr;m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 &rgr;A with an aperture size less than 50 &mgr;m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.

Abstract: A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.

Abstract: A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 &mgr;m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 &rgr;A with an aperture size less than 50 &mgr;m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.

Abstract: Low-k dieclectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.

Abstract: A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.

Abstract: A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 &mgr;m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 &rgr;A with an aperture size less than 50 &mgr;m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.