Patents by Inventor Michael P. Violette

Michael P. Violette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043525
    Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Inventors: Chiara Cerafogli, Kenneth William Marr, Brian J. Soderling, Michael P. Violette, Joshua Daniel Tomayer, James E. Davis
  • Publication number: 20210005811
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Application
    Filed: September 11, 2020
    Publication date: January 7, 2021
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10879459
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10847722
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10797237
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10777739
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10573812
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Publication number: 20200044151
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 6, 2020
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10453829
    Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Merri Lyn Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, Kevin G. Duesman, James Mathew, Michael P. Violette
  • Patent number: 10446750
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10424729
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 24, 2019
    Assignee: Ovonyx Memory Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Publication number: 20190173007
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Application
    Filed: November 20, 2018
    Publication date: June 6, 2019
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10276635
    Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Publication number: 20190027684
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Application
    Filed: September 11, 2018
    Publication date: January 24, 2019
    Inventors: Jun Liu, Michael P. Violette
  • Publication number: 20190027685
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Application
    Filed: September 11, 2018
    Publication date: January 24, 2019
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10164186
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 25, 2018
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: Jun Liu, Michael P. Violette
  • Publication number: 20180366453
    Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Merri Lyn Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, Kevin G. Duesman, James Mathew, Michael P. Violette
  • Publication number: 20180337330
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 22, 2018
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10090464
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 10008664
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette