Patents by Inventor Michael P. Violette

Michael P. Violette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of operating memory devices and electronic systems
    Patent number: 10164186
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 25, 2018
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: Jun Liu, Michael P. Violette
  • METHOD AND APPARATUS FOR REDUCING CAPACITANCE OF INPUT/OUTPUT PINS OF MEMORY DEVICE
    Publication number: 20180366453
    Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Merri Lyn Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, Kevin G. Duesman, James Mathew, Michael P. Violette
  • RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE
    Publication number: 20180337330
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 22, 2018
    Inventors: Jun Liu, Michael P. Violette
  • Buried low-resistance metal word lines for cross-point variable-resistance material memories
    Patent number: 10090464
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Phase change memory cell with constriction structure
    Patent number: 10008664
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Resistive memory architectures with multiple memory cells per access device
    Patent number: 9997701
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: June 12, 2018
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Jun Liu, Michael P. Violette
  • METHODS OF OPERATING MEMORY DEVICES AND ELECTRONIC SYSTEMS
    Publication number: 20180138404
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Jun Liu, Michael P. Violette
  • PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE
    Publication number: 20180138399
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 17, 2018
    Inventors: Jun Liu, Michael P. Violette
  • PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE
    Publication number: 20180138398
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 17, 2018
    Inventors: Jun Liu, Michael P. Violette
  • Thyristor random access memory device and method
    Patent number: 9954075
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak, Michael P. Violette
  • Methods of forming memory devices having electrodes comprising nanowires
    Patent number: 9871196
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: Jun Liu, Michael P. Violette
  • Memory device having self-aligned cell structure
    Patent number: 9773839
    Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES
    Publication number: 20170263865
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Jun Liu, Michael P. Violette
  • Buried low-resistance metal word lines for cross-point variable-resistance material memories
    Patent number: 9666800
    Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • METHODS OF FORMING MEMORY DEVICES HAVING ELECTRODES COMPRISING NANOWIRES
    Publication number: 20170104156
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 13, 2017
    Inventors: Jun Liu, Michael P. Violette
  • RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE
    Publication number: 20170069838
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 9, 2017
    Inventors: Jun Liu, Michael P. Violette
  • THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD
    Publication number: 20170025517
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
    Type: Application
    Filed: October 3, 2016
    Publication date: January 26, 2017
    Inventors: Sanh D. Tang, John K. Zahurak, Michael P. Violette
  • Memory devices having electrodes comprising nanowires
    Patent number: 9525131
    Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: December 20, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Resistive memory architectures with multiple memory cells per access device
    Patent number: 9472755
    Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: October 18, 2016
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Jun Liu, Michael P. Violette
  • Thyristor random access memory device and method
    Patent number: 9461155
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 4, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak, Michael P. Violette