Abstract: Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers, an overlying and underlying layer, on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or VSS to a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or VCC to a source of a P-channel FET transistor.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure.

Abstract: A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory metal silicide layer disposed on the nitrogen-rich Ti layer.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers—an overlying and underlying refractory metal nitride layer—on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: A static random access memory cell comprising a first inverter including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second inverter including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first inverter being cross-coupled with the second inverter, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first inverter; a second access transistor having an active terminal connected to the second inverter; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers-an overlying and underlying layer-on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract: A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: An intermediate semiconductor device for use in making surface channel MOS transistors is disclosed. The intermediate semiconductor device includes a semiconductor substrate having a top surface, a bottom surface, a plurality of doped isolation regions and a first surface channel. A first dielectric layer overlies a first portion of the top surface of the semiconductor substrate and a portion of at least one of the plurality of doped isolation regions. A first polysilicon layer overlies the first dielectric layer, and a second dielectric layer overlies the first polysilicon layer and a second portion of the top surface of the semiconductor substrate. The second dielectric layer is overlaid with a second polysilicon layer.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory metal silicide layer disposed on the nitrogen-rich Ti layer.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.