Abstract: A device may include a sensor, a sampling unit, and an interpolator. The sensor may be configured to sense motion and output a sensed signal. The sampling unit may be configured to sample the sensed signal with a sensor clocking signal to generate a plurality of sampled values. The interpolator may be coupled to the sampling unit and may be configured to receive the plurality of sampled values, the sensor clocking signal, and a reference clocking signal external to the device. The interpolator may be configured to interpolate the plurality of sampled values based on the reference clocking signal and further based on the sensor clocking signal to generate a plurality of output values.

Abstract: A device includes a proof mass of a sensor, capacitive elements, an electrode circuitry, a time multiplexing circuitry, a sense circuitry, and a force feedback circuitry. The proof mass moves from a first position to a second position responsive to an external actuation. The capacitive elements change capacitive charge in response thereto. The electrode circuitry coupled to the capacitive elements generates a charge signal. The time multiplexing circuitry pass the charge signal during a sensing time period and prevents the charge signal from passing through during a forcing time period. The sense circuitry generates a sensed signal from the charge signal. The force feedback circuitry applies a charge associated with the sensed signal to the electrode circuitry during the forcing time period. The electrode circuitry applies the charge received from the force feedback circuitry to the capacitive elements, moving the proof mass from the second position to another position.

Abstract: A gas sensor device with temperature uniformity is presented herein. In an implementation, a device includes a complementary metal-oxide semiconductor (CMOS) substrate layer, a dielectric layer and a gas sensing layer. The dielectric layer is deposited on the CMOS substrate layer. Furthermore, the dielectric layer includes a temperature sensor and a heating element coupled to a heat transfer layer associated with a set of metal interconnections. The gas sensing layer is deposited on the dielectric layer.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

Abstract: A RF-synchronization system includes a laser that creates pulse trains for synchronization. A modulation means transfers the timing information of the pulse train into an amplitude modulation of an optical or electronic system. A synchronization module changes the driving frequency of the modulation means until it reaches a phase-locked state with the pulse train.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

Abstract: A clock and data recovery system acquires a clock embedded in an input data stream by detecting the occurrence of transitions in the input data stream falling into a predetermined phase zone of a sample clock used to sample the input data stream. A control circuit counts how many evaluation intervals have at least one transition in the predetermined phase zone. The control circuit determines if lock is achieved according to the count. If it is determined that lock is not achieved, an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of evaluation intervals having one or more transitions in the predetermined phase zone is below a level indicating lock.

Abstract: A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted.

Abstract: A technique for expanding an input signal includes receiving the input signal at a first node of a voltage expander and generating a plurality of expanded signals on different outputs of the voltage expander responsive to the input signal. In certain embodiments, each of the expanded signals has a different magnitude at a respective fixed offset from the input signal.

Abstract: A RF-synchronization system includes a laser that creates pulse trains for synchronization. A modulation means transfers the timing information of the pulse train into an amplitude modulation of an optical or electronic system. A synchronization module changes the driving frequency of the modulation means until it reaches a phase-locked state with the pulse train.

Abstract: A clock and data recovery system acquires a clock embedded in an input data stream by detecting the occurrence of transitions in the input data stream falling into a predetermined phase zone of a sample clock used to sample the input data stream. A control circuit counts how many evaluation intervals have at least one transition in the predetermined phase zone. The control circuit determines if lock is achieved according to the count. If it is determined that lock is not achieved, an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of evaluation intervals having one or more transitions in the predetermined phase zone is below a level indicating lock.

Abstract: Described are methods and modules for reducing the phase noise generated in a fractional-N frequency synthesizer. The methods are based on swapping phase signals to achieve the same average delay for each phase signal path, compensation and resynchronization of phase signals and shuffling of digital-to-analog unit elements used to produce specific quantization levels. One method is based on digital gain compensation used to correct for frequency-dependent error arising from differences between horizontal slicing quantization techniques and conventional vertical slicing techniques. Also described are a combined phase detector and DAC module and a method for extending its range.