Abstract: An optical sensor including a MEMS structure, and a grating coupled resonating structure positioned adjacent to the MEMS structure, the grating coupled resonating structure comprising an interrogating grating coupler configured to direct light towards the MEMS structure. The interrogating grating coupler is two dimensional, and the interrogating grating coupler and the MEMS structure form an optical resonant cavity.

Abstract: A system for performing atomic force measurements including: a sensor including: a beam having a first side and a second side, the beam including a tip positioned on a surface of the first side for interacting with a sample; and a grating structure positioned adjacent the second side of the beam, the grating structure including an interrogating grating coupler configured to direct light towards the beam; a light source optically coupled to an input of the sensor for inputting light; and an analyser coupled to an output of the sensor; wherein the beam and the interrogating grating coupler form a resonant cavity, a movement of the beam modulates the light source and the analyser determines a deflection of the beam according to the modulated light.

Abstract: An apparatus for detecting a deflection of a beam, the apparatus comprising a beam having a first side and a second side; and a grating structure positioned adjacent the second side of the beam, the grating structure including an interrogating grating coupler configured to direct light towards the beam; wherein the beam and the interrogating grating coupler form a resonant cavity, and light input to the resonant cavity is modulated according to the deflection of the beam.

Abstract: An optical sensor including a MEMS structure, and a grating coupled resonating structure positioned adjacent to the MEMS structure, the grating coupled resonating structure comprising an interrogating grating coupler configured to direct light towards the MEMS structure. The interrogating grating coupler is two dimensional, and the interrogating grating coupler and the MEMS structure form an optical resonant cavity.

Abstract: An apparatus for detecting a deflection of a beam, the apparatus comprising a beam having a first side and a second side; and a grating structure positioned adjacent the second side of the beam, the grating structure including an interrogating grating coupler configured to direct light towards the beam; wherein the beam and the interrogating grating coupler form a resonant cavity, and light input to the resonant cavity is modulated according to the deflection of the beam.

Abstract: An apparatus for detecting a presence of one or more analytes in a sample. The apparatus comprises a cantilever (205) and a grating coupled resonating structure (210). The cantilever (205) comprises an analyte selective coating that is selective to the one or more analytes. The grating coupled resonating structure (210) is positioned adjacent to the cantilever (205). The first grating coupled resonating structure comprises a first interrogating grating coupler (220) which together with the cantilever forms an optical resonant cavity.

Abstract: An apparatus for detecting a presence of one or more analytes in a sample. The apparatus comprises a cantilever (205) and a grating coupled resonating structure (210). The cantilever (205) comprises an analyte selective coating that is selective to the one or more analytes. The grating coupled resonating structure (210) is positioned adjacent to the cantilever (205). The first grating coupled resonating structure comprises a first interrogating grating coupler (220) which together with the cantilever forms an optical resonant cavity.

Abstract: An apparatus for detecting a presence of one or more analytes in a sample. A plurality of optical cantilevered waveguides (200a, 200b) are optically coupled to an optical circuit between an input and an output of the circuit. Each of the optical cantilevered waveguides (200a, 200b) have an analyte selective coating, at least two of the waveguides having different analyte selective coatings. A detection module (304) analyses the output of the circuit to detect the presence of analytes in the sample.

Abstract: A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.

Abstract: A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a plurality of multiply structures, each containing only a single multiply array, that each correspond to at least one element of a vector input operand. Utilizing the single multiply array, each of the plurality of multiply structures is capable of performing a multiplication operation on one element of a vector input operand and is also capable of performing a multiplication operation on multiple elements of a vector input operand concurrently. In an embodiment in which the maximum length of an element of a vector input operand is N bits, each of the plurality of multiply arrays can handle both N by N bit integer multiplication and M by M bit integer multiplication, where N is a non-unitary integer multiple of M.

Abstract: A mechanism structured to check for instruction collisions at the Dispatch Unit rather than the Completion Unit. In processors which issue multiple commands simultaneously, a flag bit is sent to the Completion Unit and attached to the instruction in the queue that follows the other in program order if they both have the same targeted address. When the instructions from position 1 and position 2 of the instruction queue are ready to issue, the Completion Unit checks position 2 for a flag bit. If there is a bit, then the instruction in position 1 is discarded and the instruction in position 2 is written to the target address. If there is no flag bit with the instruction in position 2, the instruction in position 1 is written to the target register. This method eliminates the need to compare all the targeted addresses that are associated with the rename registers. It requires two comparisons instead of a minimum of 15 comparisons.

Abstract: A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

Abstract: A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution.

Abstract: A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is executed by concatenating a suffix to the mantissa in the single-precision floating-point register and replacing the high-order bit of the exponent with a prefix selected as a function of the high-order bit, wherein the resulting mantissa and exponent form a double-precision floating-point number that is then stored to memory. A load-float-double instruction is executed by dropping the suffix from the mantissa of the double-precision floating-point number in memory, and replacing the prefix with the high-order bit, wherein the resulting mantissa and exponent form a single-precision floating-point number that is then loaded into the single-precision floating-point register.

Abstract: A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A second aspect provides a fast calculation of a function of the guard bit. Both aspects comprise means for providing an intermediate result of a floating point mathematical operation involving at least a first and a second operand and means for providing a mask indicating a position of a leading one in a mantissa of the intermediate result. In the first aspect, means for aligning a first bit of the mask to an (n+2)nd bit of the intermediate result, where n is the number of bits in a mantissa of the first or second operand, are coupled to the intermediate result providing means. In the second aspect, means for aligning a first bit of the mask to an (n+1)st bit of the intermediate result are coupled to the intermediate result providing means.

Abstract: The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit.

Abstract: A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

Abstract: A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.

Abstract: A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.

Abstract: A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction.