Abstract: A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit.

Abstract: An arithmetic unit rapidly performs an XY+B floating point operation and yields a result equivalent to truncation of the product of X and Y before adding to B. Standard circuitry produces partial products from multiplier X and multiplicand Y, and a standard adder adds the partial products to yield a sum vector and a carry vector. Meanwhile, other circuitry predicts whether a most significant digit of a sum of the sum vector and the carry vector is zero or nonzero, based on less than all bits of the multiplier X and the multiplicand Y. If the most significant digit is certainly not equal to zero, a multiplexing circuit passes to a second adder a most significant N digits of the sum vector, a most significant N digits of the carry vector, a carry bit resulting from addition an (N-1)th most significant digit and lesser significant digits of the sum vector with an (N+1)th most significant digit and less significant digits of the carry vector, and an operand B.

Abstract: The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

Abstract: An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship:Pi=yP(m,n-1) V P(n,m+7) V y'P(m+8, n+7)in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y' is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0.ltoreq.i.ltoreq.3, m=8i, and n=m+2.

Abstract: The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

Abstract: A parallel binary byte adder performs addition and subtraction on the individual bytes of an A-operand and a B-operand as well as on the entire A and B operand. An A-operand is input to a special adder circuit. A B-operand is modified in a set up logic circuit, in accordance with the specific operation to be performed, before being input to the special adder circuit. A set/mask logic generates set, mask and carry signals which are further input to the special adder circuit. The special adder circuit includes an auxiliary functions circuit and a pseudo carry circuit for generating a set of variables which are processed by a sum circuit to produce three partial results. The first partial result relates to bits 0-5 of the particular byte being processed, the second relates to bit 6, and the third relates to bit 7. A concatenation of the three partial results produces a final sum or difference of the particular byte or bytes involved.

Abstract: An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B)>0, or a second branch condition ((Q+R)-B).ltoreq.0.