Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Abstract: A router receives a request including a first memory address from a source node in a first subnet. The router translates the first memory address in the request to a second memory address that is different from the first memory address. The router sends the request including the second memory address to a target node in the second subnet.

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Abstract: A control device performs an admissions control process with a first device to determine whether the first device is authorized to communicate over the communication fabric that supports memory semantic operations.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: A requester sends, to a responding component, a request to cause the responding component to perform a computation. The requester sends, to the responding component, a delayed read indication, where the delayed read indication indicates that a result of the computation is not to be returned to the requester from the responding component until a data value at a target address of the delayed read indication has changed. The requester receives, from the responding component, an acknowledgment of the delayed read indication, and after receiving the acknowledgment, receives a response to the request without the requester sending another request to the responding component.

Abstract: A control device performs an admissions control process with a first device to determine whether the first device is authorized to communicate over the communication fabric that supports memory semantic operations.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: A system includes multiple memories. Access of at least one of the multiple memories uses an interface subsystem that includes a memory controller and a distinct media controller, the memory controller to issue a transaction-level access request. The media controller is associated with at least one memory and produces, in response to the transaction-level access request, at least one command according to a specification of the at least one memory. Data is migrated from a first of the multiple memories to a second of the multiple memories, without the data traversing through a cache memory in the processor during the migrating.

Abstract: A system includes multiple memories. Access of at least one of the multiple memories uses an interface subsystem that includes a memory controller and a distinct media controller, the memory controller to issue a transaction-level access request. The media controller is associated with at least one memory and produces, in response to the transaction-level access request, at least one command according to a specification of the at least one memory. Data is migrated from a first of the multiple memories to a second of the multiple memories, without the data traversing through a cache memory in the processor during the migrating.

Abstract: A first component associated with an access controlled memory region receives a transaction request including a protocol header from a second component. The first component sends, to the second component, a negative acknowledgment in response to determining that the second component is not authorized to access the access controlled memory region, based on information in the protocol header.

Abstract: A method includes transmitting, from a first component of an electronic device, a first transaction associated with a first sequence number to a second component of the electronic device based on a multicast protocol. The first transaction is independent of an Internet protocol. The method also includes receiving an acknowledgement message that corresponds to a positive acknowledgment message or a negative acknowledgement message. The method further includes in response to receiving the negative acknowledgement message, retransmitting the first transaction to the second component using the first sequence number based on the multicast protocol.

Abstract: According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.

Abstract: An example implementation in accordance with an aspect of the present disclosure includes an address translation table of a transparent router. In response to an add service request to add a service to at least a portion of a memory system, a first address to be affected by the service is identified. An affected entry of an address translation table of the transparent router is also identified. The affected entry corresponds to a data path including the first address. The affected entry is modified to cause its corresponding data path to point to a second address associated with the service.

Abstract: The present disclosure provides an electronic device that includes a lower device configured to process local input/output communications between the electronic device and a host, wherein the lower device is stateless. The electronic device also includes a memory comprising a data flow identifier used to associate a data flow resource of the host with a data flow resource corresponding to the lower device. A data packet sent from the lower device to the host includes the data flow identifier.

Abstract: In some examples, a media controller includes a buffer and controller circuitry. The controller circuitry may receive, from a memory device linked to the media controller, an indication of a number of memory subunits that the memory device is divided into. The controller circuitry may also allocate, within the buffer, a number of logical memory buffers for the memory device greater than the number of memory subunits and indicate to a memory controller that a number of memory units accessible for the memory device is the number of logical memory buffers.

Abstract: In an example implementation according to aspects of the present disclosure, a computing system includes a memory resource having a plurality of memory resource regions and a plurality of computing resources. The plurality of computing resources are communicatively coupleable to the memory resource. Each computing node may include a native memory management unit to manage a native memory on the computing resource and a memory resource memory management unit to manage the memory resource region of the memory resource associated with the computing resource.

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Abstract: A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

Abstract: A router receives a request including a first memory address from a source node in a first subnet. The router translates the first memory address in the request to a second memory address that is different from the first memory address. The router sends the request including the second memory address to a target node in the second subnet.