Patents by Inventor Michael R. Ouellette

Michael R. Ouellette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
    Patent number: 11295829
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
    Patent number: 10971243
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
    Patent number: 10692584
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
    Patent number: 10628376
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
  • Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
    Patent number: 10628375
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
  • Arbitration for memory diagnostics
    Patent number: 10622090
    Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, Kevin W. Gorman, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette
  • BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER
    Publication number: 20200075119
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Aravindan J. BUSI, John R. GOSS, Paul J. GRZYMKOWSKI, Krishnendu MONDAL, Kiran K. NARAYAN, Michael R. OUELLETTE, Michael A. ZIEGERHOFER
  • Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
    Patent number: 10553302
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER
    Publication number: 20190378587
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Aravindan J. BUSI, John R. GOSS, Paul J. GRZYMKOWSKI, Krishnendu MONDAL, Kiran K. NARAYAN, Michael R. OUELLETTE, Michael A. ZIEGERHOFER
  • Memory built-in self-test (MBIST) test time reduction
    Patent number: 10490296
    Abstract: Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 26, 2019
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Michael R. Ouellette, Deepak I. Hanagandi, Aravindan J. Busi, Kiran K. Narayan, Michael A. Ziegerhofer
  • METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A-CHIP (SOC)
    Publication number: 20190332571
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Inventors: Thomas B. CHADWICK, JR., Michael R. OUELLETTE, Nancy H. PRATT
  • METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A-CHIP (SOC)
    Publication number: 20190332570
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Thomas B. CHADWICK, JR., Michael R. OUELLETTE, Nancy H. PRATT
  • Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
    Patent number: 10423570
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
  • Method and system for enumerating digital circuits in a system-on-a-chip (SOC)
    Patent number: 10394752
    Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas B. Chadwick, Jr., Michael R. Ouellette, Nancy H. Pratt
  • ARBITRATION FOR MEMORY DIAGNOSTICS
    Publication number: 20190035486
    Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Aravindan J. BUSI, Kevin W. GORMAN, Deepak I. HANAGANDI, Kiran K. NARAYAN, Michael R. OUELLETTE
  • Arbitration for memory diagnostics
    Patent number: 10153055
    Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, Kevin W. Gorman, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette
  • Failure analysis and repair register sharing for memory BIST
    Patent number: 10014074
    Abstract: A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Krishnendu Mondal, Deepak I. Hanagandi, Michael R. Ouellette, Valerie H. Chickanosky
  • BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER
    Publication number: 20180061509
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 1, 2018
    Inventors: Aravindan J. BUSI, John R. GOSS, Paul J. GRZYMKOWSKI, Krishnendu MONDAL, Kiran K. NARAYAN, Michael R. OUELLETTE, Michael A. ZIEGERHOFER
  • BUILT-IN SELF-TEST (BIST) ENGINE CONFIGURED TO STORE A PER PATTERN BASED FAIL STATUS IN A PATTERN MASK REGISTER
    Publication number: 20180053566
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Aravindan J. BUSI, John R. GOSS, Paul J. GRZYMKOWSKI, Krishnendu MONDAL, Kiran K. NARAYAN, Michael R. OUELLETTE, Michael A. ZIEGERHOFER
  • Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
    Patent number: 9881694
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer