Abstract: A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer and subsequent wafers running on the wafer manufacturing line are adjusted according to the offset value.

Abstract: An apparatus that improves Built-In-Self-Test (BIST) flexibility. A compilable address magnitude comparator facilitates BIST testing of different size memory arrays without requiring customization of the BIST controller. The compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller be compilable. The compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses not existing in the memory. The BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. The BIST controller is able to test memory arrays without regard for their particular size. A single BIST controller can be used to test multiple memory arrays of different sizes in the ASIC, reducing device complexity.

Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

Abstract: An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of outputs. Each output provides an output value indicative of whether a storage location associated with an applied address is passing or failing. The integrated circuit further includes a shared built-in self-test (BIST) and repair system coupled to all of the plurality of inputs and all of the plurality of outputs. The shared BIST and repair system applies addresses and data to the plurality of inputs to test the plurality of memory arrays for failing storage locations.

Abstract: A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers.

Abstract: A method of assigning bits to redundant regions for variable bit redundancy region boundaries in a compliable memory such as a 1-port SRAM is provided. Methods include allocating bits between the redundant regions in nearly equal proportions while minimizing the amount of chip real estate consumed by the memory. Methods also includes allocating bits in equal portions between redundant regions while occupying slightly more memory chip real estate. Methods also allocate bits into redundant regions with a simplified procedure which may or may not allocate bits into the redundant regions in equal proportions. All of the methods allow the total number of memory bits in the complied memory to be re-defined while maintaining the same allocation characteristics for each method. Accordingly, the methods allow efficient use of redundant memory bits while also conserving chip real estate or offering simplified allocation steps.

Abstract: Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated.

Abstract: A structure and method for performing on-chip test runs and repairs of a memory chip. In the first test run and repair, a BIST circuit obtains the original combined repair solution from a fuse bay on the memory chip, runs the first test run for the memory chip, obtains a first test-run repair solution, and combines the original combined repair solution and the first test-run repair solution to obtain the latest/first combined repair solution. Then, an exclusive-OR gate is used to compare the first combined repair solution and the original combined repair solution to obtain a first new repair solution, which is programmed into the fuses of the fuse bay. As a result, the fuse bay stores the first combined repair solution. In the second test run and repair, a similar process is performed, and so on. As a result, any number of test runs and repairs can be performed on-chip for the memory chip.

Abstract: A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.

Abstract: Multiple fuse decompression serial bitstreams support an auxiliary fuseblow capability utilizing on-chip storage and providing a composite capability of embedded memory address/data failure information. A multiple repair capability has an improved compression algorithm to compress fuse data with system level soft-set redundancy, and lends itself to self-repair design, and to provide repairs for temperature sensitive fails. An instruction based tester interface in a fuse control provides shift loaded instructions in which the sequence of test and fuse repair operations is variable to provide flexibility in the manufacturing, test and repair operations.

Abstract: An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of outputs. Each output provides an output value indicative of whether a storage location associated with an applied address is passing or failing. The integrated circuit further includes a shared built-in self-test (BIST) and repair system coupled to all of the plurality of inputs and all of the plurality of outputs. The shared BIST and repair system applies addresses and data to the plurality of inputs to test the plurality of memory arrays for failing storage locations.

Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

Abstract: A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.

Abstract: A system and method for merging multiple fuse decompression serial bitstreams to support an auxiliary fuseblow capability utilizing on-chip storage and providing a composite capability of embedded memory address/data failure information. The present invention provides a multiple repair capability having an improved compression algorithm to compress fuse data with system level soft-set redundancy, and lends itself to self-repair design, and to provide repairs for temperature sensitive fails. An instruction based tester interface in a fuse control provides shift loaded instructions in which the sequence of test and fuse repair operations is variable to provide flexibility in the manufacturing, test and repair operations.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.

Abstract: A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

Abstract: A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.