Abstract: Described are implants for placing in a body, tools for delivering the implants, and systems and methods for using implants and tools for placing in a body and more particularly to nasal implants, tools for delivering nasal implants, and systems and methods for using such implants and tools. A tool may include a hand-held implant delivery device that cuts, holds, moves, orients, inserts, or shapes an implant. An implant may be a biodegradable, longitudinal implant that may be oriented for implantation by an implant delivery device.

Abstract: A pump for pumping fluid includes a tube platen, a plunger, a bias member, inlet and outlet valves, an actuator mechanism, a position sensor, and a processor. The plunger is configured for actuation toward and away from the infusion-tube when the tube platen is disposed opposite to the plunger. The tube platen can hold an intravenous infusion tube. The bias member is configured to urge the plunger toward the tube platen.

Abstract: The application relates to a compound having Formula X: which modulates the activity of HER2 and/or a mutant thereof, and/or EGFR and/or a mutant thereof, a pharmaceutical composition comprising the compound, and a method of treating or preventing a disease in which HER2 and/or a mutant thereof, and/or EGFR and/or a mutant thereof, plays a role.

Abstract: An exemplary compounding method of controlling a compounding device to prepare an admixture of at least two distinct material sources can include examining material source solutions for incompatibility of the ingredients and operating a first and a second pump to prevent one of the incompatible source solutions from entering a common flow path. The processing method can detect degradation of a fluid line by evaluating one or more of calibration error rate data, cumulative volumetric flow data, or cumulative pump operation data. The processing method can also selectively transfer a first group of source solutions using the first pump, receiving pump data from one or more sensors that sense actions of the pumps, applying fluid correction factors and calculating discrete pump movements, the pump movements being indicative of an amount of source solution displacement by a pump, and operating the pumps to selectively dispense the source solution amounts according to a preparation order.

Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Abstract: An improved firearm includes in some embodiments a gas block of an indirect impingement system mounted on the barrel near the firing chamber to provide gas at a higher pressure for moving the piston that moves the bolt carrier. Some embodiments include low frictions rails on which the bolt carrier moves within the upper receiver. The higher gas pressure and the reduced friction from the rails reduce the required stroke of the piston, allowing a shorter firearm to be constructed. In some embodiments, mating elements, such as pins and corresponding openings, on the upper receiver and the lower receiver, align and provide additional structural strength to the upper and lower receiver.

Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Abstract: Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.

Abstract: Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.

Abstract: A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.

Abstract: A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.

Abstract: Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.

Abstract: An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables.

Abstract: A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters.

Abstract: Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells.

Abstract: Meshed touchscreen pattern. A conductive pattern implemented within a touchscreen (e.g., using indium tin oxide (ITO) such as may be deposited on a substrate composed of polyester or some other material) provides paths for signals traveling through the touchscreen. By monitoring these signal in accordance with some means (e.g., cross point detection, zone detection, etc.) an estimate may be made as to a location of user's interaction with the touchscreen (e.g., finger or stylus touching of the touchscreen). The conductive pattern includes a number of conductors aligned in various directions (e.g., row and column conductors) across the touchscreen, and they are separated by a dielectric layer (e.g., air, SiO2, or any other desirable dielectric layer). The conductors include a great deal of interlacing and meshing as achieved by spurs, extensions, and/or protrusions (e.g., of any desired shape) extending from one conductor into an adjacent conductor within the conductive pattern.

Abstract: A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters.

Abstract: An adaptive weighting method for layout optimization differentiates different priorities by assigning the weight of a higher priority (pi) to be multiple of the weight of a lower priority (pi?1) where W(pi)=mi % W(pi?1. To avoid numerical imprecision, this method keeps the total cost in the objective function within a trustable range by scaling the initial weights in the objectives, while maintaining relativity, to produce the scaled weights.

Abstract: A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.

Abstract: Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.