Abstract: A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.

Abstract: An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

Abstract: A method for making a bipolar integrated circuit structure in a semiconductor substrate. A layer of insulating material having an implantation opening is formed on the upper surface of the semiconductor substrate. A polysilicon layer is formed in the implantation opening. A doping material is implanted into the polysilicon-filled opening. The doping material is diffused into the substrate material from the polysilicon-filled opening.

Abstract: A three-dimensional CMOS integrated circuit structure in which two complementary field effect transistors are fabricated in vertical alignment with one another, and in which both transistors are single crystal and share a common crystal lattice structure and form a single unitary crystalline structure.

Abstract: Localized epitaxial growth of GaAs from a silicon monocrystalline substrate to provide a three-dimensional Si-GaAs structure and method. The silicon has an insulating layer deposited thereover and a window is opened through the layer to expose a small area of the underlying silicon from which silicon is epitaxially grown until the window is nearly full whereupon a thin buffer layer such as germanium is epitaxially grown over the epi-silicon to fill the window. Al.sub.x Ga.sub.1-x As (where x.gtoreq.0) is then locally epitaxially grown from the buffer layer and it grows laterally as well as vertically to cover the surrounding insulating layer surface and provide a site for high frequency electronics.