Abstract: Disclosed herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, that are inhibitors of Polo Like Kinase 4 (PLK4). Also disclosed herein are pharmaceutical compositions comprising the compounds of Formula (I), or pharmaceutically acceptable salts thereof, and one or more pharmaceutically acceptable excipients. Further disclosed herein are methods of treating cancer in a subject in need thereof, comprising administering to the subject an amount of a compound of Formula (I), or a pharmaceutically acceptable salt thereof.

Abstract: A multiphase composite lubricant for a railway lubricant stick that can be used in both low and high temperature applications. The composition of the multiphase composite lubricant includes an amount of a lubricant, an amount of a thermoplastic lattice components that forms a lattice structure, and a polymer extender.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

Abstract: Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.

Abstract: An ironing system includes a ram, a sensor system, and a punch nose. The ram includes a ram body and a ram nose, and the ram includes an inner surface that defines an inner chamber. The punch nose is connected to the ram nose via the sensor, and the sensor is configured to detect a force on the punch nose during an ironing process. An adaptor may be coupled to the inner surface of the ram, and the adaptor may support the sensor on the ram body.

Abstract: Disclosed herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, that are inhibitors of Polo Like Kinase 4 (PLK4). Also disclosed herein are pharmaceutical compositions comprising the compounds of Formula (I), or pharmaceutically acceptable salts thereof, and one or more pharmaceutically acceptable excipients. Further disclosed herein are methods of treating cancer in a subject in need thereof, comprising administering to the subject an amount of a compound of Formula (I), or a pharmaceutically acceptable salt thereof.

Abstract: Disclosed herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, that are inhibitors of Polo Like Kinase 4 (PLK4). Also disclosed herein are pharmaceutical compositions comprising the compounds of Formula (I), or pharmaceutically acceptable salts thereof, and one or more pharmaceutically acceptable excipients. Further disclosed herein are methods of treating cancer in a subject in need thereof, comprising administering to the subject an amount of a compound of Formula (I), or a pharmaceutically acceptable salt thereof.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

Abstract: A can redraw and ironing system includes a ram, a punch, and a sensor system. The ram includes a ram body and a ram nose. The punch is supported on the ram nose and is configured to engage a metal blank during an ironing process. The sensor system includes a first sensor that detects a total force on the ram and a second sensor that detects a force on the ram nose.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Methods, apparatuses, and systems related to scheduling internal operations are described. An apparatus detects a condition associated with repeated accesses to a memory address and/or region. In response to detection of the condition, the apparatus generates a scheduling output that secures a scheduled duration of inactivity for commanded operations. The apparatus initiates execution of one or more internal operations during the scheduled duration.

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.