Abstract: A method and system for micro-betting. One or more micro-bets can be electronically placed with respect to one or more micro-events associated with an event during a round of micro-betting. One or more wages with respect to the micro-bet(s) can be managed and controlled during the round of micro-betting. The wager(s) can be managed and controlled remote from electronically placing the micro-bet(s) during the round of micro-betting. Additionally, a portion of a profit can be automatically obtained with respect to the round of micro-bets in exchange for the aforementioned managing and controlling of the wager(s) with respect to the micro-bet(s) during the round of micro-betting.

Abstract: A method and system for micro-betting. One or more micro-bets can be electronically placed with respect to one or more micro-events associated with an event during a round of micro-betting. One or more wages with respect to the micro-bet(s) can be managed and controlled during the round of micro-betting. The wager(s) can be managed and controlled remote from electronically placing the micro-bet(s) during the round of micro-betting. Additionally, a portion of a profit can be automatically obtained with respect to the round of micro-bets in exchange for the aforementioned managing and controlling of the wager(s) with respect to the micro-bet(s) during the round of micro-betting.

Abstract: A positioning, communication, and detection system designed to provide a three dimensional location of an object, navigation tools, and bidirectional surface-to-subsurface communications, and methods of using the system. The system can include one or multiple transmitters comprising electromagnetic beacons, software defined radio receivers with an associated processing unit and data acquisition system, and magnetic antennas. The system may use theoretical calculations, scale model testing, signal processing, and sensor data.

Abstract: A positioning system designed to provide a three dimensional location of an object. The system can include one or more multiple transmitters or electromagnetic beacons, software defined radio receivers with an associated processing unit and data acquisition system, and magnetic antennas. The system applies theoretical calculations, scale model testing, signal processing, and sensor data to operate.

Abstract: A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current in the pull-up circuit to a low value so as to detect shorts because the shorts will cause the active wordline voltage level to drop, while a wordline without shorts will operate well. A GIDL (Gate Induced Drain Leakage) reduction circuit may be used as a pull-up circuit connected to supply a bias voltage to the wordline driver associated with a wordline being tested for shorts or other defects. A test signal may be selectively generated during testing so as to supply a lower strength voltage output of the GIDL circuit (the VccpRDec output) as the bias voltage to the wordline driver.

Abstract: A positioning, communication, and detection system designed to provide a three dimensional location of an object, navigation tools, and bidirectional surface-to-subsurface communications, and methods of using the system. The system can include one or multiple transmitters comprising electromagnetic beacons, software defined radio receivers with an associated processing unit and data acquisition system, and magnetic antennas. The system may use theoretical calculations, scale model testing, signal processing, and sensor data.

Abstract: A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current in the pull-up circuit to a low value so as to detect shorts because the shorts will cause the active wordline voltage level to drop, while a wordline without shorts will operate well. A GIDL (Gate Induced Drain Leakage) reduction circuit may be used as a pull-up circuit connected to supply a bias voltage to the wordline driver associated with a wordline being tested for shorts or other defects. A test signal may be selectively generated during testing so as to supply a lower strength voltage output of the GIDL circuit (the VccpRDec output) as the bias voltage to the wordline driver.

Abstract: A positioning system designed to provide a three dimensional location of an object. The system can include one or more multiple transmitters or electromagnetic beacons, software defined radio receivers with an associated processing unit and data acquisition system, and magnetic antennas. The system applies theoretical calculations, scale model testing, signal processing, and sensor data to operate.

Abstract: A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.

Abstract: A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current in the pull-up circuit to a low value so as to detect shorts because the shorts will cause the active wordline voltage level to drop, while a wordline without shorts will operate well. A GIDL (Gate Induced Drain Leakage) reduction circuit may be used as a pull-up circuit connected to supply a bias voltage to the wordline driver associated with a wordline being tested for shorts or other defects. A test signal may be selectively generated during testing so as to supply a lower strength voltage output of the GIDL circuit (the VccpRDec output) as the bias voltage to the wordline driver.

Abstract: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.

Abstract: A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and second capacitor are each configured in series for individual respective coupling between a first digit line and a second digit line. The first and second pass transistors are further configured for respective control by first and second wordlines. The memory cell further includes an interconnection formed on a cell plate conductor between a terminal end of the first capacitor and a terminal end of the second capacitor. Furthermore, the interconnection is electrically isolated from other portions of the cell plate conductor.

Abstract: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.

Abstract: A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current in the pull-up circuit to a low value so as to detect shorts because the shorts will cause the active wordline voltage level to drop, while a wordline without shorts will operate well. A GIDL (Gate Induced Drain Leakage) reduction circuit may be used as a pull-up circuit connected to supply a bias voltage to the wordline driver associated with a wordline being tested for shorts or other defects. A test signal may be selectively generated during testing so as to supply a lower strength voltage output of the GIDL circuit (the VccpRDec output) as the bias voltage to the wordline driver.

Abstract: A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.

Abstract: Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.

Abstract: A memory array having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.

Abstract: Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.

Abstract: Testing methods and facilitating circuitry permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.

Abstract: Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.