Patents by Inventor Michael Shore
Michael Shore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210074357Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Michael A. Shore
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Patent number: 10867675Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.Type: GrantFiled: June 11, 2018Date of Patent: December 15, 2020Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Michael A. Shore
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Publication number: 20200388325Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.Type: ApplicationFiled: June 4, 2019Publication date: December 10, 2020Applicant: Micron Technology, Inc.Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
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Patent number: 10854270Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.Type: GrantFiled: July 25, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Scott E. Smith, Michael A. Shore
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Publication number: 20200349995Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Shore, Jiyun Li
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Publication number: 20200312384Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.Type: ApplicationFiled: April 1, 2019Publication date: October 1, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Shinichi Miyatake, Michael A. Shore, Adam J. Grenzebach
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Patent number: 10770127Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.Type: GrantFiled: February 6, 2019Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Michael A. Shore, Jiyun Li
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Publication number: 20200251158Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael A. Shore, Jiyun Li
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Patent number: 10600472Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.Type: GrantFiled: August 20, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Huy T. Vo, Patrick Mullarkey, Jeffrey P. Wright, Michael A. Shore
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Publication number: 20200066105Abstract: A method and system for micro-betting. One or more micro-bets can be electronically placed with respect to one or more micro-events associated with an event during a round of micro-betting. One or more wages with respect to the micro-bet(s) can be managed and controlled during the round of micro-betting. The wager(s) can be managed and controlled remote from electronically placing the micro-bet(s) during the round of micro-betting. Additionally, a portion of a profit can be automatically obtained with respect to the round of micro-bets in exchange for the aforementioned managing and controlling of the wager(s) with respect to the micro-bet(s) during the round of micro-betting.Type: ApplicationFiled: May 14, 2018Publication date: February 27, 2020Inventors: Michael Shore, Alfonso Chan, Luis Ortiz, Kermit Lopez
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Patent number: 10497420Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.Type: GrantFiled: May 8, 2018Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Scott E. Smith, Michael A. Shore
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Publication number: 20190348100Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.Type: ApplicationFiled: May 8, 2018Publication date: November 14, 2019Inventors: Scott E. Smith, Michael A. Shore
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Publication number: 20190347904Abstract: A method and system for micro-betting. One or more micro-bets can be electronically placed with respect to one or more micro-events associated with an event during a round of micro-betting. One or more wages with respect to the micro-bet(s) can be managed and controlled during the round of micro-betting. The wager(s) can be managed and controlled remote from electronically placing the micro-bet(s) during the round of micro-betting. Additionally, a portion of a profit can be automatically obtained with respect to the round of micro-bets in exchange for the aforementioned managing and controlling of the wager(s) with respect to the micro-bet(s) during the round of micro-betting.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: Michael Shore, Alfonso Chan, Luis Ortiz, Kermit Lopez
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Publication number: 20190348102Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.Type: ApplicationFiled: July 25, 2019Publication date: November 14, 2019Inventors: Scott E. Smith, Michael A. Shore
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Publication number: 20190019553Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.Type: ApplicationFiled: June 11, 2018Publication date: January 17, 2019Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Michael A. Shore
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Publication number: 20180358084Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.Type: ApplicationFiled: August 20, 2018Publication date: December 13, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Scott J. Derner, HUY T. VO, PATRICK MULLARKEY, JEFFREY P. WRIGHT, MICHAEL A. SHORE
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Patent number: 10127971Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.Type: GrantFiled: May 1, 2017Date of Patent: November 13, 2018Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Huy T. Vo, Patrick Mullarkey, Jeffrey P. Wright, Michael A. Shore
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Publication number: 20180315466Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.Type: ApplicationFiled: May 1, 2017Publication date: November 1, 2018Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Huy T. Vo, Patrick Mullarkey, Jeffrey P. Wright, Michael A. Shore
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Patent number: 9672939Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.Type: GrantFiled: October 20, 2014Date of Patent: June 6, 2017Assignee: Micron Technology, Inc.Inventor: Michael A. Shore
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Publication number: 20150082106Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.Type: ApplicationFiled: October 20, 2014Publication date: March 19, 2015Inventor: Michael A. Shore