Abstract: A product design tradeoff method is provided. A transfer function, which generates an output in response to an input is obtained. A type of optimization to be performed is identified and the input to the transfer function is perturbed in order to achieve the type of optimization identified. Output information representing the output of the transfer function is then generated to provide the user with the result of the optimization. Generating the output information comprises generating a sensitivity matrix. The sensitivity matrix comprises a plurality of sensitivity values that indicates a relationship between a change in input versus a change in output, wherein each of the sensitivity values provides a corresponding numerical value for comparing an effect of the change in the input versus the change in the output.

Abstract: A silicide processing method for a thin film SOI device including depositing a metal or an alloy on a gate and a source/drain structure formed in a silicon-on-insulator film, reacting the metal or alloy at a first temperature with the silicon-on-insulator film to form a first alloy, etching the unreacted layer of the metal (or alloy) selectively, depositing a Si film on the first alloy, reacting the Si film at a second temperature to form a second alloy, and etching the unreacted layer of the Si film selectively.

Abstract: An exemplary embodiment of the invention is directed to a method for performing quality function deployment for a system having a plurality of levels. The method includes obtaining a plurality of first level critical to quality parameters and obtaining a plurality of first level key control parameters. A first level quality matrix is generated identifying an effect at least one first level key control parameter has on at least one first level critical to quality parameter. The first level key control parameters are arranged into a first group and a second group. A second level quality matrix is generated for the first group. The second level quality matrix includes second level critical to quality parameters corresponding to the first group of first level key control parameters and a second level key control parameter. The second level quality matrix identifies an effect said second level key control parameter has on at least one second level critical to quality parameter.

Abstract: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

Abstract: A method of generating quality matrices indicating a relationship between critical to quality characteristics and key control parameters for levels of a process. A plurality of rows of a first matrix are designated as critical to quality characteristics and a plurality of columns of the first matrix are designated as key control parameters. Each critical to quality characteristic is assigned a critical to quality weight. An interaction weight is assigned between at least one critical to quality characteristic and at least one key control parameter. A score is then generated for at least one key control parameter in response to said critical to quality weight and said interaction weight.

Abstract: A back-plane for a semiconductor device, includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.

Abstract: A foot mop includes a cover member configured and contoured to receive and overlay a substantial portion of a user's shoe sole. The cover member has an interior surface, an exterior surface and a continuous free edge that defines an opening. On the interior surface of the cover member are a plurality of peripherally disposed snaps adjacent the free edge for matably engaging snaps on an adhesive strip peripherally mounted about the shoe. The exterior surface of the cover member includes a sponge layer with a plurality of mop like fibers mounted thereover for absorbing liquids. The device also includes a wall mounted storage device for draining and collecting fluids adhering to the cover member.

Abstract: A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.

Abstract: A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafers to form a bond between the first and second wafers, and detaching a portion of the first wafer from the second wafer. Thus, a device, such as a back-plane for a semiconductor device, formed by the method includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.

Abstract: Method and apparatus for cascading devices wherein the output voltage is greater than the individual voltage capacity of the circuit components. The cascadable switch contains transistors connected so that the source and gate voltages on a given transistor are derived from the drain and source voltages of the preceding stage in the cascade. Depletion mode devices are utilized in one embodiment of the invention, while level shifter circuits are incorporated into another embodiment.

Abstract: An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Abstract: The present invention concerns single-gate and double-gate field effect transistors having a sidewall source contact and a sidewall drain contact, and methods for making such field effect transistors. The channel of the present field effect transistors is raised with respect to the support structure underneath and the source and drain regions form an integral part of the channel.