Abstract: A multiple input linear voltage regulator includes an output port configured to supply an output voltage to one or more processor components; a first regulating transistor operable to receive a first input voltage from a first supply and provide a first regulated voltage range to the output port; a second regulating transistor operable to receive a second input voltage from a second supply and provide a second regulated voltage range to the output port, wherein the first input voltage is different from the second input voltage; and a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage.

Abstract: Embodiments herein describe circuitry and techniques to implement shunt current control of an on-chip voltage regulator of a memory storage system using hardware components and computer software tools. Disclosed embodiments provide an on-chip voltage regulator with enhanced performance, reducing power requirements, and minimizing noise and voltage fluctuations of the regulator output, based on a cache activity signal produced by a cache controller.

Abstract: On-die control for active interposer voltage regulation according to an example includes receiving, by a switch in voltage regulation circuitry in an active interposer, an input voltage. Voltage regulation control circuitry in a chip die connected to the active interposer controls the voltage regulation circuitry, including causing the switch to couple the input voltage to one or more passive components of the voltage regulation circuitry in the active interposer. The voltage regulation circuitry regulates the input voltage to generate a regulated output voltage that is output to the chip die.

Abstract: Two-stage processor voltage regulation according to an example includes receiving, by a buck switching regulator circuit formed in an active interposer that is positioned on a module, a voltage. The buck switching regulator circuit outputs to each of one or more chip dies positioned on the active interposer based on the received voltage, a first regulated voltage. Each of one or more on-chip voltage regulators in each of the one or more chip dies generates based on the first regulated voltage, a respective second regulated voltage.

Abstract: Global processor core voltage control through integrated voltage regulation includes outputting, from an integrated voltage regulator to a processor core based on a global input voltage, a regulator output voltage. A power efficiency monitor and control circuit receives voltage control parameters from the integrated voltage regulator. The power efficiency monitor and control circuit controls a global voltage regulator based on the received voltage control parameters to cause an adjustment to the global input voltage.

Abstract: Alternative design selection in integrated circuit generation includes generating an integrated circuit design including a first set of components configured to optimize a first metric, a second set of components configured to optimize a second metric different than the first metric, and a first selection component configured to select between use of the first set of components or the second set of components. An integrated circuit is caused to be generated based on the integrated circuit design.

Abstract: Distributed voltage regulation by current sharing including receiving an input voltage on a chip; and regulating the input voltage using current sharing through a plurality of distributed low voltage dropout micro regulators to produce regulated voltage, each low voltage dropout micro regulator including an additional degenerative pass device providing gain reduction with improved current sharing and local feedback.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

Abstract: An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

Abstract: An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

Abstract: An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

Abstract: A device and a signal processing method that can monitor human memory performance by recognizing and characterizing high-gamma (65-250 Hz) and beta (14-30 Hz) band oscillations in the left Brodmann Area 40 (BA40) of the brain that correspond with the strength of memory encoding or correct recall. The signal processing method detects high-gamma and beta band oscillations in the electrical signals recorded from left BA40, and quantifies the spectral content, power, duration, onset, and offset of the oscillations. The oscillation's properties are used to classify the subject's memory performance on the basis of a comparison with the subject's prior human memory performance and the properties of the corresponding oscillations. A report of the subject's current memory performance can be utilized in a closed loop brain stimulation device that serves the purpose of enhancing human memory performance.

Abstract: A device and a signal processing method that can monitor human memory performance by recognizing and characterizing high-gamma (65-250 Hz) and beta (14-30 Hz) band oscillations in the left Brodmann Area 40 (BA40) of the brain that correspond with the strength of memory encoding or correct recall. The signal processing method detects high-gamma and beta band oscillations in the electrical signals recorded from left BA40, and quantifies the spectral content, power, duration, onset, and offset of the oscillations. The oscillation's properties are used to classify the subject's memory performance on the basis of a comparison with the subject's prior human memory performance and the properties of the corresponding oscillations. A report of the subject's current memory performance can be utilized in a closed loop brain stimulation device that serves the purpose of enhancing human memory performance.

Abstract: Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.

Abstract: Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.

Abstract: A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.