Patents by Inventor Michael Sperling
Michael Sperling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210091753Abstract: Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Publication number: 20210089104Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Michael Sperling, Pawel Owczarczyk, Akil Khamisi Sutton, Erik English
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Publication number: 20210089071Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Erik English, Akil Khamisi Sutton, Pawel Owczarczyk, Michael Sperling
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Patent number: 10931269Abstract: Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.Type: GrantFiled: October 3, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Pawel Owczarczyk, Chad Andrew Marquart, Douglas Malone
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Publication number: 20210025926Abstract: Techniques for a slope detector for voltage droop monitoring are described herein. An aspect includes receiving an input voltage by a circuit. Another aspect includes producing, by the circuit, a filtered offset voltage based on the input voltage. Another aspect includes determining whether the input voltage is lower than the filtered offset voltage. Yet another aspect includes, based on the input voltage being lower than the filtered offset voltage, indicating an imminent voltage droop condition in the input voltage.Type: ApplicationFiled: July 23, 2019Publication date: January 28, 2021Inventors: ERIK ENGLISH, MICHAEL SPERLING
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Patent number: 10833653Abstract: Aspects of the invention include a circuit including a power circuit having an amplifier, a resistor, a current source, and a first node, one end of the resistor being configured to couple to a power supply, the first node being coupled to an opposite end of the resistor, a first input terminal of the amplifier, and the current source. A voltage sensitive circuit includes a logic gate coupled to both a second input terminal of the amplifier and an output terminal of the amplifier at a second node.Type: GrantFiled: September 23, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Patent number: 10797712Abstract: A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.Type: GrantFiled: September 6, 2019Date of Patent: October 6, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pawel Owczarczyk, Michael Sperling, Miguel E. Perez
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Patent number: 10742202Abstract: Techniques for autozero to an offset value for a slope detector for voltage droop monitoring are described herein. An aspect includes generating a first offset voltage by a circuit. Another aspect includes generating a second offset voltage by the circuit, the second offset voltage being distinct from the first offset voltage. Another aspect includes, based on a first comparator of the circuit entering an autozero mode, connecting a first terminal of the first comparator to the first offset voltage. Another aspect includes connecting a second terminal of the first comparator to the second offset voltage. Yet another aspect includes performing an autozero operation in the first comparator, wherein a trip point of the first comparator is set to a difference between the first offset voltage and the second offset voltage by the autozero operation.Type: GrantFiled: July 23, 2019Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik English, Michael Sperling
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Patent number: 10644497Abstract: Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.Type: GrantFiled: May 17, 2017Date of Patent: May 5, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kennedy K. Cheruiyot, Paul D. Muench, Michael A. Sperling, Michael R. Whalen
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Patent number: 10601216Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.Type: GrantFiled: December 15, 2016Date of Patent: March 24, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul D. Muench, Miguel E. Perez, George E. Smith, III, Michael A. Sperling
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Patent number: 10296637Abstract: Systems, devices, and methods include generating, for at least one search term of a query, a first expanded set of search terms based on at least one related term of the at least one search term obtained from a knowledge base, generating a second expanded set of search terms by applying a statistical model to the search terms of the first expanded set based on terms included in an electronic document corpus stored in an electronic data storage, and generating a third expanded set of search terms based on search terms in the first and second expanded sets. For each search term of the third expanded set, a term score is determined based on occurrence of the search term in the electronic document. The term scores are combined to create a document score for the electronic document.Type: GrantFiled: August 23, 2016Date of Patent: May 21, 2019Assignee: Stroz Friedberg, LLCInventor: Michael Sperling
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Publication number: 20180337669Abstract: Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.Type: ApplicationFiled: May 17, 2017Publication date: November 22, 2018Inventors: Kennedy K. Cheruiyot, Paul D. Muench, Michael A. Sperling, Michael R. Whalen
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Patent number: 10069409Abstract: A distributed voltage regulator includes multiple micro-regulators disposed in a corresponding set of circuit sectors of an integrated circuit. Each micro-regulator provides current to the corresponding circuit sector at a current injection point. The regulator also includes a control module configured to receive feedback signals corresponding to a one or more sense points within each circuit sector and provide a control signal to each micro-regulator. The control module limits load-sharing imbalance within the plurality of micro-regulators. A voltage regulator with multiple sense points includes a micro-regulator that provides current at a current injection point, and a control module that receives feedback signals corresponding to a plurality of sense points and provides a control signal to the micro-regulator. The micro-regulator may comprise a charge pump that provides a local reference voltage that enables the micro-regulator to suppress local voltage drooping during feedback transitions (e.g.Type: GrantFiled: September 13, 2016Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: John F. Bulzacchelli, Michael A. Sperling, Zeynep Toprak Deniz
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Patent number: 10033270Abstract: An apparatus for providing a local reference voltage for a voltage regulator includes a reference capacitor configured to provide the local reference voltage, a charge pump configured to push current to, or pull current from, the reference capacitor according to one or more control inputs received by the charge pump, and a boosting circuit configured to add or subtract a discrete quantity of charge to the reference capacitor according to one or more boosting control signals. A boosting control circuit may be configured to disconnect a boosting capacitor from the reference capacitor during a first phase of a control cycle and connect the boosting capacitor to the reference capacitor during a second phase of the control cycle. The boosting capacitor may be pre-charged (to add charge) or discharged (to subtract charge) during the first phase of the control cycle. A corresponding method is also disclosed herein.Type: GrantFiled: October 26, 2016Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: John F. Bulzacchelli, Seongwon Kim, Michael A. Sperling, Zeynep Toprak Deniz
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Publication number: 20180175608Abstract: An analog multiplexer includes a plurality of voltage-protecting transmission gate circuits to select an input voltage signal among different input signals. Each voltage-protecting transmission gate circuit includes a pass gate pFET interconnected between an input pFET and an output pFET, as well as a parallel pass gate nFET. The pFET includes a first source/drain connected in series with the input pFET. A second source/drain is connected in series with the output pFET. A pFET gate receives a gate select signal that operates the transmission gate circuit in a blocking mode, a first passing mode, or a second passing mode. The nFET includes a first nFET source/drain connected to the input pFET to form a main input terminal that receives the input voltage signal. A second nFET source/drain is connected to the output pFET to form a main output terminal that outputs an output voltage based on the operating mode.Type: ApplicationFiled: December 15, 2016Publication date: June 21, 2018Inventors: Paul D. Muench, Miguel E. Perez, George E. Smith, III, Michael A. Sperling
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Publication number: 20180115238Abstract: An apparatus for providing a local reference voltage for a voltage regulator includes a reference capacitor configured to provide the local reference voltage, a charge pump configured to push current to, or pull current from, the reference capacitor according to one or more control inputs received by the charge pump, and a boosting circuit configured to add or subtract a discrete quantity of charge to the reference capacitor according to one or more boosting control signals. A boosting control circuit may be configured to disconnect a boosting capacitor from the reference capacitor during a first phase of a control cycle and connect the boosting capacitor to the reference capacitor during a second phase of the control cycle. The boosting capacitor may be pre-charged (to add charge) or discharged (to subtract charge) during the first phase of the control cycle. A corresponding method is also disclosed herein.Type: ApplicationFiled: October 26, 2016Publication date: April 26, 2018Inventors: John F. Bulzacchelli, Seongwon Kim, Michael A. Sperling, Zeynep Toprak Deniz
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Publication number: 20180076708Abstract: A distributed voltage regulator includes multiple micro-regulators disposed in a corresponding set of circuit sectors of an integrated circuit. Each micro-regulator provides current to the corresponding circuit sector at a current injection point. The regulator also includes a control module configured to receive feedback signals corresponding to a one or more sense points within each circuit sector and provide a control signal to each micro-regulator. The control module limits load-sharing imbalance within the plurality of micro-regulators. A voltage regulator with multiple sense points includes a micro-regulator that provides current at a current injection point, and a control module that receives feedback signals corresponding to a plurality of sense points and provides a control signal to the micro-regulator. The micro-regulator may comprise a charge pump that provides a local reference voltage that enables the micro-regulator to suppress local voltage drooping during feedback transitions (e.g.Type: ApplicationFiled: September 13, 2016Publication date: March 15, 2018Inventors: John F. Bulzacchelli, Michael A. Sperling, Zeynep Toprak Deniz
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Publication number: 20180060323Abstract: Systems, devices, and methods include generating, for at least one search term of a query, a first expanded set of search terms based on at least one related term of the at least one search term obtained from a knowledge base, generating a second expanded set of search terms by applying a statistical model to the search terms of the first expanded set based on terms included in an electronic document corpus stored in an electronic data storage, and generating a third expanded set of search terms based on search terms in the first and second expanded sets. For each search term of the third expanded set, a term score is determined based on occurrence of the search term in the electronic document. The term scores are combined to create a document score for the electronic document.Type: ApplicationFiled: August 23, 2016Publication date: March 1, 2018Inventor: Michael Sperling
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Patent number: 9882552Abstract: A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.Type: GrantFiled: September 25, 2015Date of Patent: January 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Friend, Grant P. Kesselring, Michael A. Sperling, James D. Strom
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Patent number: 9871527Abstract: A phase-locked loop (PLL) circuit, sense amplifier circuit, and method of operating a sense amplifier circuit are disclosed. The sense amplifier circuit comprises first and second operational amplifiers, each operational amplifier respectively comprising a non-inverting input terminal, an inverting input terminal, and an output stage comprising a current gating circuit having two current gating input terminals, the output stage coupled with an output terminal, the output terminal providing a feedback signal to the inverting input terminal. The input voltage signal is received across the non-inverting input terminals of the first and second operational amplifiers, and is received across the two current gating input terminals of each of the first and second operational amplifiers, wherein the sense amplifier circuit generates a sense voltage signal across the output terminals of the first and second operational amplifiers.Type: GrantFiled: January 30, 2017Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Friend, Grant P. Kesselring, Michael A. Sperling, James D. Strom