Abstract: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Abstract: A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer.

Abstract: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Abstract: A method and system determines deformations in a substrate in the manufacturing of semiconductor devices. At least one property of vertical deformations of the substrate is measured at a plurality of locations on the substrate. Afterward, an automatic computation of horizontal deformations is determined based on the measured properties of vertical deformations with a model for the deformation behavior of the substrate.

Abstract: A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.

Abstract: An integrated circuit, which is formed on a semiconductor substrate and which comprises front-end-of-line processed electronic elements and a back-end-of-line processed wiring on top of the electronic elements. The wiring interconnects the electronic elements. The integrated circuit further comprises a highly UV-absorbing layer between the electronic elements and the wiring.

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

Abstract: The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).

Abstract: During a selective oxidation of gate structures that includes a polycrystalline silicon layer and a tungsten layer, which is known per se, a vapor deposition of tungsten oxide is prevented or at least greatly reduced by a special process. The gate structure is acted on by a hydrogen-containing, nonaqueous inert gas before and, if appropriate, after a treatment step with a hydrogen/water mixture.

Abstract: The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).

Abstract: A process is described for depositing silicon nitride, in which the temperature in a furnace is set to from 600° C. to 645° C. The silicon nitride formed in this way is permeable to small molecules, such as in particular hydrogen molecules, yet nevertheless retains its etching selectivity with respect to silicon dioxide.

Abstract: A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for low-pressure chemical vapor deposition or oxidation. A heating system is particularly useful for heating a reactor in which a plurality of wafers is held perpendicularly to the reactant gas flowing direction that is parallel to the longitudinal axis of the reactor, to enable a deposition or oxidation reaction. The heating system is adapted to change the reactor temperature during the process. In addition, a method heats a reactor to enable a reaction. Preferably, each of a plurality of reactor zones, into which the reactor is divided in a direction parallel to the reactant gas flowing direction, is heated at a different temperature profile indicating the temperature of this specific zone versus time. Thereby, the in-plane uniformity of deposited or oxidized layers can be largely improved.

Abstract: A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for low-pressure chemical vapor deposition or oxidation. A heating system is particularly useful for heating a reactor in which a plurality of wafers is held perpendicularly to the reactant gas flowing direction that is parallel to the longitudinal axis of the reactor, to enable a deposition or oxidation reaction. The heating system is adapted to change the reactor temperature during the process. In addition, a method heats a reactor to enable a reaction. Preferably, each of a plurality of reactor zones, into which the reactor is divided in a direction parallel to the reactant gas flowing direction, is heated at a different temperature profile indicating the temperature of this specific zone versus time. Thereby, the in-plane uniformity of deposited or oxidized layers can be largely improved.