Patents by Inventor Michael Todd Wyant
Michael Todd Wyant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071828Abstract: Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies from a semiconductor wafer without using a blade. The methods include a plasma etch process utilizing metal structures formed on a back side of the wafer as masks to remove a portion of the semiconductor wafer from the back side. The portion removed by the plasma etch process corresponds to the scribe lines between the semiconductor dies. The plasma etch process terminates at a dielectric layer formed on a front side of the wafer. The dielectric layer may be severed to complete the separation process. Moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer that has been severed.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventor: Michael Todd Wyant
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Publication number: 20240055313Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Inventors: Michael Todd Wyant, Matthew John Sherbin, Christopher Daniel Manack, Patrick Francis Thompson, You Chye How
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Patent number: 11837518Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.Type: GrantFiled: August 26, 2020Date of Patent: December 5, 2023Assignee: Texas Instruments IncorporatedInventors: Michael Todd Wyant, Matthew John Sherbin, Christopher Daniel Manack, Patrick Francis Thompson, You Chye How
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Publication number: 20230387036Abstract: A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer. The method also includes performing a wafer expansion process that separates individual semiconductor dies from the wafer after the laser ablation process.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Inventors: Michael Todd Wyant, Joseph O. Liu, Christopher Daniel Manack
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Publication number: 20230274978Abstract: In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Michael Todd WYANT, Joseph LIU, Christopher Daniel MANACK
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Publication number: 20230260839Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU
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Patent number: 11676829Abstract: In a described example, an apparatus includes: a process chamber configured for a pressure greater than one atmosphere, having a device chuck configured to support electronic devices that are mounted on package substrates and partially covered in mold compound, the electronic devices spaced from one another by saw streets; and a saw in the process chamber configured to cut through the mold compound and package substrates in the saw streets to separate the molded electronic devices one from another.Type: GrantFiled: December 31, 2020Date of Patent: June 13, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Byron Harry Gibbs, Michael Todd Wyant
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Patent number: 11664276Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.Type: GrantFiled: November 30, 2018Date of Patent: May 30, 2023Assignee: Texas Instruments IncorporatedInventors: Matthew John Sherbin, Michael Todd Wyant, Christopher Daniel Manack, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Ming Zhu, Joseph O. Liu
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Publication number: 20230134102Abstract: A photo alignment structure is provided that includes a wafer having scribe lines defined therein in a top planar surface of the wafer. An alignment structure is disposed on a top planar surface of the wafer longitudinally aligned with a portion of selected scribe lines, where the alignment structure is comprised of metal layers. A slot is defined along a longitudinal axis of the alignment structure in at least one of the metal layers.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Stephen Arlon Meisner, James Thomas Hallowell, Michael Todd Wyant
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Publication number: 20230040267Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: ApplicationFiled: October 5, 2022Publication date: February 9, 2023Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11482442Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: GrantFiled: February 24, 2021Date of Patent: October 25, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11469141Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: GrantFiled: August 7, 2018Date of Patent: October 11, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Publication number: 20220208571Abstract: In a described example, an apparatus includes: a process chamber configured for a pressure greater than one atmosphere, having a device chuck configured to support electronic devices that are mounted on package substrates and partially covered in mold compound, the electronic devices spaced from one another by saw streets; and a saw in the process chamber configured to cut through the mold compound and package substrates in the saw streets to separate the molded electronic devices one from another.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Byron Harry Gibbs, Michael Todd Wyant
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Publication number: 20220068744Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.Type: ApplicationFiled: August 26, 2020Publication date: March 3, 2022Inventors: Michael Todd WYANT, Matthew John SHERBIN, Christopher Daniel MANACK, Patrick Francis THOMPSON, You Chye HOW
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Patent number: 11171031Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.Type: GrantFiled: July 23, 2018Date of Patent: November 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano
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Publication number: 20210210440Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: Christopher Daniel Manack, Qiao Chen, Michael Todd Wyant, Matthew John Sherbin, Patrick Francis Thompson
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Publication number: 20210183683Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 10840211Abstract: A packaged semiconductor device includes at least one semiconductor die having circuitry with circuit nodes coupled to bond pads that have bonding features thereon. A plurality of leads or lead terminals include at least metal bars, wherein the plurality of leads or lead terminals are exclusive of any saw marks. The semiconductor die is flipchip attached with a bonded connection between respective bonding features and respective leads or lead terminals.Type: GrantFiled: February 15, 2019Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bradley Andrew Glasscock, Michael Todd Wyant, Christopher Daniel Manack
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Publication number: 20200266133Abstract: A packaged semiconductor device includes at least one semiconductor die having circuitry with circuit nodes coupled to bond pads that have bonding features thereon. A plurality of leads or lead terminals include at least metal bars, wherein the plurality of leads or lead terminals are exclusive of any saw marks. The semiconductor die is flipchip attached with a bonded connection between respective bonding features and respective leads or lead terminals.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Bradley Andrew Glasscock, Michael Todd Wyant, Christopher Daniel Manack
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Publication number: 20200176314Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU