Patents by Inventor Michael Todd Wyant

Michael Todd Wyant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200075386
    Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, SADA HIROYUKI, SHOICHI IRIGUCHI, GENKI YANO
  • Publication number: 20200051860
    Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 13, 2020
    Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
  • Publication number: 20200027772
    Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO
  • Patent number: 8883567
    Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Todd Wyant, Patricia Sabran Conde, Vikas Gupta, Rajiv Dunne, Emerson Mamaril Enipin
  • Publication number: 20130256852
    Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Todd Wyant, Patricia Sabran Conde, Vikas Gupta, Rajiv Dunne, Emerson Mamaril Enipin