Abstract: A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Abstract: According to one or more embodiments of the present invention, a computer-implemented method includes determining, for a first sector from multiple sectors of a clock mesh of a semiconductor circuit, a set of mesh wires. The method further includes generating tapping point candidates, selecting a first combination of tapping points, and performing an analog electrical simulation of a clock signal. The simulation includes feeding the clock signal into the clock mesh via the first combination of tapping points via a clock signal transmitter, and measuring delays for the clock signal to reach a set of measuring nodes. The maximum delay from the measured delays is selected, and, in response to the maximum delay being less than a previous delay value, the first combination of tapping points is used to connect sector buffers from the first sector to the clock mesh.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: Aspects of the present disclosure relate to adaptive mesh wiring. A clock signal is provided to a clock mesh area, wherein the clock mesh area includes a plurality of wires configured in a grid. A pair of loads with impermissible skew within the clock mesh area is identified based on a threshold value. A mesh network area partition enclosing the pair of loads with impermissible skew is determined. Modifications are then made to the mesh network area partition to attempt to reduce skew. In some embodiments, a wire width of a portion of wires included in the mesh network area partition is increased. In some embodiments, a wire is added in between two wires present in the mesh network area partition.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The first duty cycle correction circuit receives the input signal. The first duty cycle correction circuit generates a first intermediate signal. The device includes a first programmable delay circuit. The first programmable delay circuit is controlled by a first delay control signal. The first programmable delay circuit receives the first intermediate signal. The first programmable delay circuit generates an output signal. The device includes a second duty cycle correction circuit. The second duty cycle correction circuit receives the input signal. The second duty cycle correction circuit generates a second intermediate signal. The device includes a second programmable delay circuit. The second programmable delay circuit generates a reference signal. The device includes a skew control arrangement operable for generating the first delay control signal.

Abstract: A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

Abstract: The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

Abstract: A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Abstract: A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The first duty cycle correction circuit receives the input signal. The first duty cycle correction circuit generates a first intermediate signal. The device includes a first programmable delay circuit. The first programmable delay circuit is controlled by a first delay control signal. The first programmable delay circuit receives the first intermediate signal. The first programmable delay circuit generates an output signal. The device includes a second duty cycle correction circuit. The second duty cycle correction circuit receives the input signal. The second duty cycle correction circuit generates a second intermediate signal. The device includes a second programmable delay circuit. The second programmable delay circuit generates a reference signal. The device includes a skew control arrangement operable for generating the first delay control signal.

Abstract: The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

Abstract: The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

Abstract: According to one or more embodiments, a skew control circuit for controlling the skew between at least two digital signals is provided. The skew control circuit may include a pulse generator that may generate a pulse with a pulse width, whereby the pulse width of the pulse may depend on a skew between edges of the two digital signals. The skew control circuit may also include a pulse width sensor that may output a pulse width value that represents the pulse width of the generated pulse. The skew control circuit may further include a skew controller that may adjust a delay of the at least one of the digital signals based on a target skew value and the pulse width value.