Patents by Inventor Michael W. Murphy
Michael W. Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11741041Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.Type: GrantFiled: February 10, 2022Date of Patent: August 29, 2023Assignee: APPLE INC.Inventors: Ian P. Shaeffer, Eric C. Gaertner, John T Orchard, Michael W. Murphy, Ronald P. Songco, Corey N. Axelowitz, Brett W. Degner
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Patent number: 11726835Abstract: A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.Type: GrantFiled: May 12, 2020Date of Patent: August 15, 2023Assignee: APPLE INC.Inventors: Michael W. Murphy, Gopal Thirumalai Narayanan, Deepak K. Mishra, Andre M. Glover, Sreenivas Tallam, Hardik K. Doshi
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Publication number: 20230019372Abstract: Various techniques related to authenticating and verifying the integrity of data received by a computer system from an external source (such as a sensor) are disclosed. Hardware circuits are disclosed that, along with the computer processor, allow for error-checking and authentication of data received by the computer system. For instance, the hardware circuits may generate a separate authentication code that can be compared to the authentication code in the data itself to determine whether or not the message is authentic and whether or not there is an error in the data. The disclosed techniques reduce the processing requirements of a computer system and can be implemented using simple hardware circuit designs.Type: ApplicationFiled: July 13, 2021Publication date: January 19, 2023Inventors: Paul A. Baker, Michael W. Murphy, Mark P. Colosky, James E. Zmuda, Jangwon Lee, Kevin C. Gotze, Peter Louis Bielawski
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Publication number: 20220269640Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.Type: ApplicationFiled: February 10, 2022Publication date: August 25, 2022Inventors: Ian P. Shaeffer, Eric C. Gaertner, John T. Orchard, Michael W. Murphy, Ronald P. Songco, Corey N. Axelowitz, Brett W. Degner
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Patent number: 11281619Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.Type: GrantFiled: March 11, 2020Date of Patent: March 22, 2022Assignee: Apple Inc.Inventors: Ian P. Schaeffer, Eric C. Gaertner, John T. Orchard, Michael W. Murphy, Ronald P. Songco, Corey N. Axelowitz, Brett W. Degner
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Publication number: 20200356417Abstract: A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.Type: ApplicationFiled: May 12, 2020Publication date: November 12, 2020Inventors: Michael W. MURPHY, Gopal Thirumalai NARAYANAN, Deepak K. MISHRA, Andre M. GLOVER, Sreenivas TALLAM, Hardik K. DOSHI
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Publication number: 20200311012Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.Type: ApplicationFiled: March 11, 2020Publication date: October 1, 2020Inventors: Ian P. Schaeffer, Eric C. Gaertner, John T. Orchard, Michael W. Murphy, Ronald P. Songco, Corey N. Axelowitz, Brett W. Degner
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Patent number: 9740645Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.Type: GrantFiled: April 20, 2015Date of Patent: August 22, 2017Assignee: Apple Inc.Inventors: Michael W. Murphy, Joshua P. de Cesare, Timothy R. Paaske
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Patent number: 9111039Abstract: The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network.Type: GrantFiled: August 29, 2012Date of Patent: August 18, 2015Assignee: APPLE II 'C.Inventor: Michael W. Murphy
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Publication number: 20150227476Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Applicant: Apple Inc.Inventors: Michael W. Murphy, Joshua P. de Cesare, Timothy R. Paaske
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Patent number: 9015396Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.Type: GrantFiled: September 18, 2012Date of Patent: April 21, 2015Assignee: Apple Inc.Inventors: Michael W. Murphy, Joshua P. de Cesare, Timothy R. Paaske
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Patent number: 9015384Abstract: Methods and apparatus for efficiently transporting data through network tunnels. In one embodiment, a tunneled device advertises certain capabilities to peer devices of a network, and discovers capabilities of peer devices of the network. In a second embodiment, each device of a tunneled network derives a network parameter from a transit protocol parameter for use in data networking.Type: GrantFiled: May 2, 2012Date of Patent: April 21, 2015Assignee: Apple Inc.Inventors: Niel D. Warren, Girault W. Jones, Jr., Raymond B. Montagne, Matthew X. Mora, Brett D. George, Michael W. Murphy, William P. Cornelius
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Patent number: 8976799Abstract: A high-speed I/O interface that allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages (“VDMs”) for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O (“CIO”) interface. The devices can be designed to provide synchronization (time value, frequency, and phase) among a network of routers, with signal paths of several meters, thereby providing an accurate time base suitable for exacting audiovisual applications.Type: GrantFiled: September 27, 2008Date of Patent: March 10, 2015Assignee: Apple Inc.Inventors: Paul A. Baker, Michael W. Murphy, Eric Werner Anderson, Colin Whitby-Strevens, David Ferguson, Keith Diefendorff, Ron Hochsprung, William Cornelius
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Publication number: 20140082242Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.Type: ApplicationFiled: September 18, 2012Publication date: March 20, 2014Applicant: APPLE INC.Inventors: Michael W. Murphy, Joshua P. de Cesare, Timothy R. Paaske
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Publication number: 20140068131Abstract: The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Applicant: APPLE INC.Inventor: Michael W. Murphy
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Patent number: 8463881Abstract: A high-speed optical interface for connecting computers to external I/O devices allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages (“VDMs”) for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O (“CIO”) interface. Standard PCIe bridges are modified to support peer-to-peer communications, allowing greater exploitation of the capabilities of PCIe.Type: GrantFiled: September 27, 2008Date of Patent: June 11, 2013Assignee: Apple Inc.Inventors: Paul A. Baker, Michael W. Murphy, Eric Werner Anderson, Colin Whitby-Strevens, David Ferguson, Keith Diefendorff, Ron Hochsprung, William Cornelius
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Publication number: 20120284434Abstract: Methods and apparatus for efficiently transporting data through network tunnels. In one embodiment, a tunneled device advertises certain capabilities to peer devices of a network, and discovers capabilities of peer devices of the network. In a second embodiment, each device of a tunneled network derives a network parameter from a transit protocol parameter for use in data networking.Type: ApplicationFiled: May 2, 2012Publication date: November 8, 2012Inventors: NIEL D. WARREN, Girault W. Jones, JR., Raymond B. Montagne, Matthew X. Mora, Brett D. George, Michael W. Murphy, William P. Cornelius
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Patent number: 8288046Abstract: A current sensor assembly that monitors current flow through segments of a fuel cell stack. The current sensor assembly includes a first plate including a first non-conductive substrate having a first conductive path therethrough and that is in electrical communication with a first segment of the fuel cell stack. A second plate includes a second non-conductive substrate having a second conductive path therethrough and that is in electrical communication with a second segment of the fuel cell stack. A first current sensor is operably disposed between the first plate and the second plate and facilitates a first current flow between the first conductive path and the second conductive path. The first current sensor generates a first current signal based on the first current flow.Type: GrantFiled: September 29, 2004Date of Patent: October 16, 2012Assignee: GM Global Technology Operations LLCInventors: Michael W Murphy, Robert L Fuss
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Patent number: D728408Type: GrantFiled: July 18, 2014Date of Patent: May 5, 2015Inventor: Michael W. Murphy
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Patent number: D744890Type: GrantFiled: July 18, 2014Date of Patent: December 8, 2015Inventor: Michael W. Murphy