Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: Auto-configuration support for a multiple processor-ready pair or FRC-master/checker pair is achieved through the use of an initialization signal issued to each agent on a bus during system reset. The agents on the bus are interconnected using a rotating interconnect scheme which causes each agent to sample a signal issued from another agent on a pin different from the pin on which the other agent issued the signal. When operating in FRC-master/checker mode, the checker agent operates as if it were the master agent, thereby checking the operation of the master agent. The initialization signal modifies the input and or output lines connected to the pins of the checker agent based on this rotating interconnect scheme, thereby ensuring the checker agent properly checks the master agent's operation.

Abstract: A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

Abstract: Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent.

Abstract: An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent.

Abstract: A computer system providing a universal architecture includes a processor card connected to a system bus of a host computer system. The processor card is adapted for insertion into a slot of the computer system and houses a processor and a bus bridge conversion device. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.

Abstract: A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.

Abstract: A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.

Abstract: A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

Abstract: A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.

Abstract: Atomicity of lock variables is preserved in a computer system in response to a request by a microprocessor for a bus lock access whether the lock variable is split between two cache lines or is within a single cache line. A non-split lock bus access which can be satisfied by a cacheable region within the same cluster as the microprocessor issuing the access is allowed to complete, regardless of whether ownership of the next level bus is available. If the non-split lock access can not be satisfied within the cluster, then ownership of the next level bus is obtained, if available, to satisfy the access. Similarly, a split lock access may complete if ownership of the second level bus can be obtained. However, a split lock access is aborted if the second level bus ownership is not available, regardless of whether a cacheable region within the same cluster can satisfy the request.

Abstract: A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.

Abstract: An apparatus for synchronously transmitting data between devices operating at different frequencies that have a P/Q integer ratio relationship. The apparatus allows one or more device(s) operating at a high frequency to synchronously exchange data with one or more device(s) operating at a low frequency. The low and high frequencies have a P/Q integer ratio relationship of:low frequency=(P/Q).times.high frequency;where P and Q represent integer values, P is less than Q, and Q is not necessarily an integer multiple of P. A P/Q clock generator generates one or both of the high and low frequency clocks according to the P/Q frequency ratio. An interface controller receives the high frequency clock and the P and Q values as inputs and generates a high-to-low data transfer signal for enabling data transfers from high frequency to low frequency devices. The interface controller also generates a low-to-high frequency data transfer signal for enabling data transfers from low to high frequency devices.

Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer.

Abstract: A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

Abstract: In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.