Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner).

Abstract: Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent.

Abstract: An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent.