Abstract: A method for facilitating regulatory compliance with respect to telephony communications is provided. The method includes: assigning, to a mobile telephone, an access number; routing a communication that relates to the assigned access number to a gateway; processing the routed communication to ensure compliance with all jurisdictional regulations, including real-time call recording and short message service (SMS) capturing for compliance archival and search, applying data loss prevention (DLP) rules, and any other suitable processing; and forwarding the processed communication to the mobile telephone. A subscriber identification module (SIM) that is associated with the access number is physically installed at the gateway. The communication may be a voice communication and/or an SMS text communication.

Abstract: A method for facilitating regulatory compliance with respect to telephony communications is provided. The method includes: assigning, to a mobile telephone, an access number; routing a communication that relates to the assigned access number to a gateway; processing the routed communication to ensure compliance with all jurisdictional regulations, including real-time call recording and short message service (SMS) capturing for compliance archival and search, applying data loss prevention (DLP) rules, and any other suitable processing; and forwarding the processed communication to the mobile telephone. A subscriber identification module (SIM) that is associated with the access number is physically installed at the gateway. The communication may be a voice communication and/or an SMS text communication.

Abstract: Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.

Abstract: Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A thermal conductive tape article is provided which is adhered to the surface of an integrated circuit device to dissipate heat from the device. The thermal conductive tape article is preferably corrugated and may have a number of configurations providing an expanded surface area. The corrugated tape article may also have a metal strip bonded to one or both sides of the tape article to form a single-faced or double-faced corrugated tape article. The tape article is preferably made of copper or aluminum.

Abstract: An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A thermal conductive tape article is provided which is adhered to the surface of an integrated circuit device to dissipate heat from the device. The thermal conductive tape article is preferably corrugated and may have a number of configurations providing an expanded surface area. The corrugated tape article may also have a metal strip bonded to one or both sides of the tape article to form a single-faced or double-faced corrugated tape article. The tape article is preferably made of copper or aluminum.