DIGITAL TEST SYSTEM AND METHOD FOR VALUE BASED DATA
Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.
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The present invention relates generally to integrated circuits, and, more particularly, to the testing of integrated circuits.
BACKGROUND OF THE INVENTIONAs integrated circuits are produced with greater and greater levels of circuit density, improved testing methodologies have become necessary. One such methodology, which implements boundary scan testing of external or internal chip networks, has become to be in general use in the industry. The most common method is elaborated in the IEEE standard 1149.1, defines a TAP (Test Access Port) to implement a set of test functions, providing test access at chip level as well as at the printed circuit board (PBC) level. While boundary scan testing is prevalent, limitations still exist. In particular, evaluation of digitally encoded values (binary/signed or two's complement) where such values are not known a-priori, presents challenges in an Automatic Test Equipment (ATE) test environment where digitally based tests are completely deterministic. It is therefore desirable to have an improved system and method for integrated circuit testing to address the aforementioned shortcomings.
SUMMARYIn one embodiment of the present invention, a logic circuit is provided. The logic circuit comprises an inequality register, a lower limit register, an upper limit register, a test data register, a test data out signal, a greater-than-or-equal compare logic block, a less-than compare logic block, wherein the inequality register comprises a plurality of bits that when programmed, enable an inequality evaluation comparing data in the test data register with data in the upper limit register and the lower limit register, and wherein the logic circuit is configured and disposed to cause the test data out signal to be asserted when data in the test data register satisfies an inequality condition.
In another embodiment of the present invention, an integrated circuit chip is provided. The integrated circuit chip comprises at least one logic core, at least one inequality indication system, and at least one test data out signal configured and disposed to output the results of the at least one inequality indication system. In another embodiment of the present invention, a method is provided for evaluating an inequality in a digital logic circuit. The method comprises programming an inequality register, programming an upper limit register, programming a lower limit register, and programming a value to be compared in a test data register.
The structure, operation, and advantages of the present invention will become further apparent upon consideration of the following description taken in conjunction with the accompanying figures (FIGs.). The figures are intended to be illustrative, not limiting.
Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity.
Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG).
Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip requiring tester dependent custom code. Embodiments of the present invention allow for arbitrary location of an MSB-to-LSB or two's complement ordered value within an address register or scan string. Embodiments of the present invention provide a greater than and less than (range checking), less than, greater than, or equality type evaluation to be performed. Such evaluations may use the entire resolution of the measurement or limit the evaluation to a set of higher (or lower) order bits. Further, the evaluation produces a quasi real-time result of the inequality comparison on one or more chip external I/O for fast pass/fail evaluation. This can enable more efficient testing, and also allows inspection of parameters that can not be predicted a priori. The following description and accompanying figures further describes embodiments of the present invention. Note that while in some examples, JTAG (IEEE 1149.1) is used, embodiments of the present invention are not limited to JTAG, and other testing schemes and boundary scan systems may be used in conjunction with embodiments of the present invention.
A less-than compare logic block (LT COMP) 114 asserts a LT signal 109 when a comparison between the data contained in the TDR register 102 and the data in the LLIM register 112 evaluates such that LLIM<TDR. Similarly, a greater-than-or-equal compare logic block (GTE COMP) 122 asserts a GT signal 125 when a comparison between the data contained in the TDR register 102 and the data in the HUM register 120 evaluates such that HUM>TDR. GTE COMP 122 asserts EQ signal 127 when a comparison between the data contained in the TDR register 102 and the data in the HUM register 120 evaluates such that HLIM=TDR. The GTE COMP 122 and LT COMP 114 may be implemented using techniques well-known in the art.
The inequality information system is configured via the INEQ register 116. Each bit is referred to as INEQX, where X represents a particular bit location within the INEQ register. For example, INEQ0 pertains to bit 0 of the INEQ register 116, and is an activation bit for the IIS 100. INEQ0 is an input used to activate the IIS when ENABLE signal 124 is asserted. When the IIS is enabled, the result of the inequality evaluation is output on the TDO signal 106. When the IIS is disabled, the TDO signal 106 functions as a normal TDO signal for a test environment, and can clock out the contents of the TDR register. Hence, the IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal. Bits INEQ1 and INEQ2 are used to configure the type of inequality from the following options:
LLIM<TDR<HUM
TDR=HUM
HUM>TDR
LLIM<TDR
The output signal LT 109 of LT COMP 114, and output signals GT 125 and EQ 127 from GTE COMP 122 are input to combining logic block 108 along with the settings of INEQ1 and INEQ2. The output 129 of combining logic block 108 is output to the TDO signal 106 (when ENABLE signal 124 is asserted).
INEQ3 and INEQ4 are used to configure the mode for the comparisons. When INEQ3 is set to 0, a binary mode is used. When INEQ3 is set to 1, a twos-complement mode is used. The INEQ4 bit indicates the TDR bits being evaluated are signed when set to 1, and unsigned when set to 0.
Bits INEQ5, INEQ6, and INEQ7 are readable bits that convey the current status of the inequality. INEQ5 is set to 1 when the EQ signal 127 is asserted, and set to 0 when the EQ signal is not asserted. INEQ6 is set to 1 when the LT signal 109 is asserted, and set to 0 when the LT signal is not asserted. INEQ7 is set to 1 when the GT signal 125 is asserted, and set to 0 when the GT signal is not asserted. In this way, the current state of an inequality evaluation can be obtained in two different ways. One way is by reading bits INEQ5-INEQ7. Another way is to monitor the state of the TDO signal 106 when the IIS is active (ENABLE 124 is asserted).
Using the TDO signal 106 to evaluate an inequality expression allows for efficient testing and is particularly well-suited for characterization applications. For example, in certain cases, analog values that may vary from device to device can be quickly checked to determine if they are in range. For example, internally, circuits may apply a current bias to the input of a latch to optimize it's sensitivity in a desired range. The current bias is established by programming a digital-to-analog-converter (DAC) register. In an embodiment of the present invention, an iterative process may be used to determine the optimal value. To quickly determine if the DAC is programmed within a specified range, the low limit register LLIM 110 and high limit register HLIM 120 are programmed with the acceptable lower and upper limits of the DAC, respectively. In this case, the value of the DAC register is placed in TDR 102 and the IIS 100 is configured to assert the TDO signal 106 when the value in TDR 102 is between the value in LLIM 112 and HLIM 120. This allows for fast testing of the DAC register to determine if it is in range. A test can be run multiple times while the TDO signal 106 is monitored to determine if the DAC register is ever set outside of acceptable limits.
Design flow 1600 may vary depending on the type of representation being designed. For example, a design flow 1600 for building an application specific IC (ASIC) may differ from a design flow 1600 for designing a standard component or from a design flow 1600 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 1610 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 1610 may include using a variety of inputs; for example, inputs from library elements 1630 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1640, characterization data 1650, verification data 1660, design rules 1670, and test data files 1685 (which may include test patterns and other testing information). Design process 1610 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 1610 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.
Design process 1610 preferably translates an embodiment of the invention as shown in
Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, certain equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.) the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application.
Claims
1. A logic circuit comprising: wherein the inequality register comprises a plurality of bits that when programmed, enable an inequality evaluation comparing data in the test data register with data in the upper limit register and the lower limit register, and wherein the logic circuit is configured and disposed to cause the test data out signal to be asserted when data in the test data register satisfies an inequality condition.
- an inequality register;
- a lower limit register;
- an upper limit register;
- a test data register;
- a test data out signal;
- a greater-than-or-equal compare logic block;
- a less-than compare logic block;
2. The logic circuit of claim 1, further comprising: wherein the lower limit mask register is configured and disposed to mask the lower limit register and wherein the upper limit mask register is configured and disposed to mask the upper limit register.
- a lower limit mask register;
- an upper limit mask register;
3. The logic circuit of claim 1, further comprising a greater-than-or-equal compare logic block, the greater-than-or-equal compare logic block configurable to operate in signed arithmetic in response to programming a bit in the inequality register.
4. The logic circuit of claim 1, further comprising a greater-than-or-equal compare logic block, the greater-than-or-equal compare logic block configurable to operate in twos-complement arithmetic in response to programming a bit in the inequality register.
5. The logic circuit of claim 1, further comprising a less-than compare logic block, the less-than compare logic block configurable to operate in signed arithmetic in response to programming a bit in the inequality register.
6. The logic circuit of claim 1, further comprising a less-than compare logic block, the less-than compare logic block configurable to operate in twos-complement arithmetic in response to programming a bit in the inequality register.
7. The logic circuit of claim 1, wherein the inequality register comprises an activation bit.
8. The logic circuit of claim 7, wherein the inequality register further comprises three readable bits that contain status information for an inequality evaluation.
9. (canceled)
10. An integrated circuit chip comprising: wherein the at least one logic core comprises a plurality of logic cores, and each logic core of the plurality of logic cores comprises an inequality indication system.
- at least one logic core;
- at least one inequality indication system;
- at least one test data out signal configured and disposed to output the results of the at least one inequality indication system; and
11. The integrated circuit chip of claim 10, wherein the at least one test data out signal comprises a test data out signal for each logic core.
12. The integrated circuit chip of claim 10, further comprising: wherein the combining module is configured and disposed to receive a signal from the inequality indication system of each logic core of the plurality of logic cores.
- a JTAG test port;
- a combining module;
- a decoding logic block;
13. The integrated circuit chip of claim 10, comprising a single, chip-level inequality indication system configured and disposed to receive a test signal from the at least one logic core.
14. The integrated circuit chip of claim 10, comprising:
- a single, chip-level inequality indication system configured and disposed to receive data from one or more scan chains; and
- a test data out signal configured and disposed to convey the evaluation of an inequality of scan chain data by the chip-level inequality indication system.
15. A method for evaluating an inequality in a digital logic circuit, comprising:
- programming an inequality register;
- programming an upper limit register;
- programming a lower limit register; and
- programming a value to be compared in a test data register.
16. The method of claim 15, further comprising monitoring a test data out signal.
17. The method of claim 15, further comprising:
- programming a lower limit mask register; and
- programming an upper limit mask register.
18. The method of claim 15, further comprising:
- reading a plurality of bits of the inequality register to retrieve status information for an inequality evaluation.
19. The method of claim 15, further comprising:
- inputting data from a scan chain into a test data register;
- programming the inequality register to evaluate an inequality wherein the value of data in the test data register is less than the value in the upper limit register and the value of data in the test data register is greater than the value in the lower limit register.
20. The method of claim 19, wherein inputting data from a scan chain into a test data register comprises inputting an ambient temperature value.
Type: Application
Filed: Sep 15, 2011
Publication Date: Mar 21, 2013
Applicant: INTERNATIONAL BUSINESS MACHINES (Armonk, NY)
Inventors: Eugene Rogers Atwood (Poughkeepsie, NY), Thomas Joseph Bardsley (Hopewell Junction, NY), Victor Moy (Hopewell Junction, NY), Michael Won (Hopewell Junction, NY)
Application Number: 13/233,374
International Classification: H03K 19/00 (20060101);