Abstract: A network system that provides for separating and isolating control of processing entities in a network interface. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. One of the processing entities operates as a hypervisor to configure control resources to isolate operation of the plurality of data processing partitions to process data transported by the network system. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing.

Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.

Abstract: A method and apparatus for mapping sessions to preassigned processing entities in a network system. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions based upon an association with a predetermined session.

Abstract: A method of performing a lookup within a network interface unit which includes providing a plurality of memory access channels, performing a multilayer lookup operation on a packet, and refining a selection of one of the plurality of memory access channels based upon the multilayer lookup operation is disclosed.

Abstract: A network system which includes a plurality of separate processing entities, an input output bus, and a network interface unit shared among the plurality of separate processing entities is disclosed. The network interface unit is coupled to the plurality of separate processing entities via the input output bus. The network interface unit has a plurality of memory access channels and each memory access channel is assigned to one processing entity.

Abstract: A network system includes a network interface unit operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. The asymmetrical data processing partitions are scalable by adding additional processing entities.

Abstract: A method of resolving mutex contention within a network interface unit which includes providing a plurality of memory access channels, and moving a thread via at least one of the plurality of memory access channels, the plurality of memory access channels allowing moving of the thread while avoiding mutex contention when moving the thread via the at least one of the plurality of memory access channels is disclosed.

Abstract: A method of resolving mutex contention within a network interface unit which includes providing a plurality of memory access channels, and moving a thread via at least one of the plurality of memory access channels, the plurality of memory access channels allowing moving of the thread while avoiding mutex contention when moving the thread via the at least one of the plurality of memory access channels is disclosed.

Abstract: An inspection device includes a movable portion, and a substantially fixed portion. The movable portion includes a plurality of bins as well as beam directors positioned between the bins. The fixed portion includes light detectors and light emitters. The light detectors are arranged to allow multiplexing of the light detectors.

Abstract: A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

Abstract: A design strategy for constructing hierarchically structured materials using nanoparticles and synthetic biopolymers has been developed. Block copolypeptides or homopolymer polyelectrolytes are used as structure-directing agents to arrange nanoparticles (composed of metals, metal non-oxides, metal oxides, or organics) into unusual microstructures, such as spheres, “apples” and “cups.” Hollow spheres can be made wherein nanoparticles of one composition are spatially oriented completely interior or exterior to nanoparticles of a second composition. These aggregates contain nanoparticles only in the shell walls, and maintain their hollowness upon calcination. These shapes can also be fabricated into films. These robust materials are anticipated to have great promise in applications that require surface catalysis, magnetic/electronic/optic properties, transport capabilities, and combinations thereof, such as drug delivery, packaging, catalysis, and sensors.

Abstract: A reorder mechanism for use with a relaxed order interconnect device. The reorder mechanism includes a buffer module and a reorder module coupled to the buffer module is disclosed. The reorder module enables movement of multiple packets between a plurality of resources. The movement of multiple packets of information has a relaxed ordering of data transfers associated with multiple packets and also a relaxed ordering of data transfers associated with any single packet.

Abstract: A method and computer program product, for providing an optimization for a most derived object during compile time are provided. The optimization determines whether a most derived class object is present during a compile time. Also, the optimization utilizes the most derived class object to obtain a location of a virtual base for the most derived class object during the compile time, and provides the virtual base of the most derived class object during the compile time. The method is executed for a constructor and/or a destructor. The constructor or destructor contains arguments which require conversion to a base type, and the conversion is performed at compile-time instead of at runtime.

Abstract: A method for scaling a network system which includes providing at least one network interface and providing a flexible association between packets and a plurality of processing entities via the plurality of memory access channels. Each network interface including a plurality of memory access channels.

Abstract: Cleats configured to retain objects secured with a packaging tie in association with packaging material.

Abstract: A method for providing access to a network interface having a plurality of memory access channels is disclosed. The network interface provides access to a plurality of processing entities. The method includes providing a network interface software hierarchy wherein the network interface software hierarchy provides access to the network interface, and associating various memory access channels with corresponding processing entities via the network interface software hierarchy so as to provide a virtualized network interface.

Abstract: A network system having a plurality of processing partitions which includes a network interface unit coupled to a plurality of processing entities is disclosed. The network interface unit includes a plurality of memory access channels. The plurality of memory access channels is virtualized. The network interface unit is shared among the plurality of processing partitions.

Abstract: A method for maximizing page locality within a networking system operationally attached to a plurality of processing entities wherein each processing entity either shares or includes a corresponding memory hierarchy wherein each memory hierarchy has a table of pages temporally managed by access from the networking system is disclosed. The method includes providing at least one memory access channel to each memory hierarchy and moving information to and from pages in the memory hierarchy of a particular processing entity via its associated memory access channels.