Abstract: A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Abstract: A process of removing holefill residue from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.

Abstract: A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material.

Abstract: A method of forming an electronic structure, including adhesively coupling a plated metallic layer (e.g. a copper layer) of a plated through hole (PTH) to holefill material (e.g., epoxy resin) distributed within the PTH. The adhesive coupling utilizes an adhesion promoter film on the plated metallic layer such that the adhesion promoter film is bonded to the resin. The adhesion promoter film may include a metallic oxide layer such as a layer containing cupric oxide and cuprous oxide, which could be formed from bathing a PTH plated with copper in a solution of sodium chlorite. The adhesion promoter film may alternatively include an organometallic layer such as a layer that includes a chemical complex of metal and an organic corrosion inhibitor. The organometallic layer could be formed from bathing the PTH in a bath of hydrogen peroxide, sulfuric acid, and the organic corrosion inhibitor.

Abstract: A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Abstract: A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.

Abstract: A method of making a circuitized substrate having plated through holes free of filler material is provided. The method includes the steps of providing a dielectric substrate having first and second opposite faces. At least one via hole is formed from one face to the other. A first electrically conductive layer is applied onto the top and bottom faces of the dielectric member and onto the side wall of the via. First layers of photoresist are applied to each layer of conductive material and entering at least partially into the via hole. The first layers of photoresist are selectively exposed and developed to remove all of the photoresist, except that photoresist which is disposed in the via holes. Thereafter, a portion of the faces of the metal coatings on the surfaces of dielectric material and any photoresist remaining in the holes extending above the layers of electrically conductive material are removed to form a planar surface thinner than the thickness of the metal in the through hole.

Abstract: A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.

Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.

Abstract: An electronic structure, and associated method of formation, in which a plated metallic layer such as a copper layer, of a plated through hole (PTH) is adhesively coupled to holefill material distributed within the PTH. The holefill material includes a resin such as an epoxy and optionally includes a particulate component such as a copper powder. The adhesive coupling is accomplished by forming an adhesion promoter film on the plated metallic layer such that the adhesion promoter film is bonded to the resin. The adhesion promoter film may include a metallic oxide layer such as layer containing cupric oxide and cuprous oxide, which could be formed from bathing the PTH in a solution of sodium chlorite. Application of a reducing solution of dimethylamine borane to the cuprous oxide layer would convert some of the cuprous oxide to cupric oxide in the metallic oxide layer.

Abstract: A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and routing out a preselected portion of the base member to form an aperture. Metallization of the dielectric member and the walls of the aperture then occurs, followed by circuitization of the surfaces of the dielectric member. Direct metallization of the aperture walls eliminates many manufacturing steps previously required to metallize the aperture walls.

Abstract: An electronic structure, and associated method of formation, in which a plated metallic layer such as a copper layer, of a plated through hole (PTH) is adhesively coupled to holefill material distributed within the PTH. The holefill material includes a resin such as an epoxy and optionally includes a particulate component such as a copper powder. The adhesive coupling is accomplished by forming an adhesion promoter film on the plated metallic layer such that the adhesion promoter film is bonded to the resin. The adhesion promoter film may include a metallic oxide layer such as layer containing cupric oxide and cuprous oxide, which could be formed from bathing the PTH in a solution of sodium chlorite. Application of a reducing solution of dimethylamine borane to the cuprous oxide layer would convert some of the cuprous oxide to cupric oxide in the metallic oxide layer.

Abstract: A method for planarizing an exposed metal surface on a substrate is provided in which surface irregularities are eliminated. A photoresist layer is first removed from the substrate. Then a conformal planarizing head is placed in contact with the metal surface while chemical etchant essentially free of abrasives is supplied to an interface between the metal substrate and the planarizing head. The surface is then planarized until it is free of irregularties.

Abstract: A technique for polishing an exposed surface of metal on a substrate to remove defects from mechanical working of metals, such as burrs and pigtails resulting from drilling, and defects from plating, such as nodules and depressions, is provided. The substrate has an exposed metal surface such as copper thereon which is to be treated to remove defects. A planarizing or polishing head, preferably a rotating roller, is provided which is continuously rotating with respect to the substrate, with the head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the head. The treating and polishing continues until the defects have been removed or reduced to an acceptable value. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used.

Abstract: A technique for chemically planarizing an exposed surface of metal on a substrate to a pre-determined thickness is provided. The substrate has an exposed metal surface such as copper circuitry on a dielectric substrate which is to be planarized. Typically, this will be circuitization extending above a photoresist layer. A planarizing head is rotated against the substrate, with the planarizing head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the planarizing head. The planarizing continues until a predetermined thickness of the metal has been reached. In circuit board manufacturing, this will form a surface co-planar with the photoresist. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.