Patents by Inventor Michael Xuefei Tang

Michael Xuefei Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8940577
    Abstract: A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 27, 2015
    Assignee: Seagate Technology LLC
    Inventors: Venkatram Venkatasamy, Ming Sun, Michael Xuefei Tang
  • Patent number: 8766230
    Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Shuiyuan Huang, Dimitar V. Dimitrov, Michael Xuefei Tang, Song S. Xue
  • Patent number: 8711608
    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 29, 2014
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
  • Patent number: 8466525
    Abstract: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: June 18, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Xiaohua Lou, Haiwen Xi, Michael Xuefei Tang
  • Patent number: 8466524
    Abstract: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: June 18, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Xiaohua Lou, Haiwen Xi, Michael Xuefei Tang
  • Patent number: 8456903
    Abstract: A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: June 4, 2013
    Assignee: Seagate Technology LLC
    Inventors: Michael Xuefei Tang, Ming Sun, Dimitar V. Dimitrov, Patrick Ryan
  • Patent number: 8422278
    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: April 16, 2013
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
  • Patent number: 8400823
    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 19, 2013
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
  • Publication number: 20130009126
    Abstract: A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Venkatram Venkatasamy, Ming Sun, Michael Xuefei Tang
  • Patent number: 8343801
    Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 1, 2013
    Assignee: Seagate Technology LLC
    Inventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
  • Patent number: 8293571
    Abstract: A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: October 23, 2012
    Assignee: Seagate Technology LLC
    Inventors: Venkatram Venkatasamy, Ming Sun, Michael Xuefei Tang
  • Patent number: 8288753
    Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
  • Patent number: 8203865
    Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: June 19, 2012
    Assignee: Seagate Technology LLC
    Inventors: Wei Tian, Insik Jin, Venugopalan Vaithyanathan, Haiwen Xi, Michael Xuefei Tang, Brian Lee
  • Patent number: 8183654
    Abstract: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: May 22, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Xiaohua Lou, Haiwen Xi, Michael Xuefei Tang
  • Publication number: 20120080317
    Abstract: A method of forming CoNiP on a substrate that includes the steps of placing a substrate in an electroplating bath, the electroplating bath containing an electroplating composition, the electroplating composition including: a nickel source; a cobalt source; and at least about 0.1 M phosphorus source; and applying a deposition current to the substrate, wherein application of the deposition current to the substrate will cause a CoNiP layer having a thickness of at least about 500 nanometers to be electrodeposited on the substrate.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Venkatram Venkatasamy, Ming Sun, Ibro Tabakovic, Michael Xuefei Tang
  • Publication number: 20120040496
    Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 16, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
  • Publication number: 20120032131
    Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 9, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
  • Patent number: 8058646
    Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: November 15, 2011
    Assignee: Seagate Technology LLC
    Inventors: Ming Sun, Michael Xuefei Tang, Insik Jin, Venkatram Venkatasamy, Philip George Pitcher, Nurul Amin
  • Publication number: 20110228597
    Abstract: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.
    Type: Application
    Filed: May 27, 2011
    Publication date: September 22, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yuankai Zheng, Xiaohua Lou, Haiwen Xi, Michael Xuefei Tang
  • Patent number: 8004875
    Abstract: A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Markus Jan Peter Siegert, Michael Xuefei Tang, Andrew John Carter, Alan Xuguang Wang