Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.

Abstract: The present invention relates to a quick response power supply switching device. It also relates to a power supply network equipped with such a switch. The electrical power supply is connected to a set of blocks, the device comprises at least one switch (3) connecting the power supply (VDD) and the block (1), the value of the power supply current passing through the switch being controlled according to the difference between the power supply voltage (VDD) at the level of the other blocks and voltage threshold. The invention applies notably to all integrated circuits of recent technology in which it is important to reduce the leakage currents of the transistors in the unused circuit parts. The invention thus applies particularly to most systems powered by cell or battery and more particularly to portable telephone circuits.

Abstract: A shared memory made on a chip based on semiconductors comprising: an integer number m, greater than one, of data buses; m address and control buses; m input/output interfaces, each input/output interface being connected to one of the m data buses and to one of the m address and control buses; an integer number p, greater than one, of memory banks, each memory bank comprising: a memory, comprising a data input/output and an address and control input controlled by each of the address and control buses; a block of m switches, each of the m switches being connected on the one hand to a memory data bus, said memory data bus being connected to the data input/output of the memory, and on the other hand to one of the m data buses.

Abstract: The present invention relates to a method for limiting the throughput of a communication in a meshed network, comprising the following steps: allocating fixed paths to communications likely to be established on the network; identifying the communications likely to take a mesh segment; allocating respective throughput quotas to the identified communications such that the sum of these quotas is less than or equal to a nominal throughput of said segment; and measuring the throughput of each communication at the input of the network and suspending the communication when its quota is reached.

Abstract: A circuit having at least one processor and a microprogrammed machine for processing the data which enters or leaves the processor in order to input or output the data into/from the circuit in compliance with a communication protocol.

Abstract: The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.

Abstract: An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.

Abstract: A circuit having at least one processor and a microprogrammed machine for processing the data which enters or leaves the processor in order to input or output the data into/from the circuit in compliance with a communication protocol.

Abstract: The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.

Abstract: The present invention relates to a method for limiting the throughput of a communication in a meshed network, comprising the following steps: allocating fixed paths to communications likely to be established on the network; identifying the communications likely to take a mesh segment; allocating respective throughput quotas to the identified communications such that the sum of these quotas is less than or equal to a nominal throughput of said segment; and measuring the throughput of each communication at the input of the network and suspending the communication when its quota is reached.

Abstract: The present invention relates to a shared memory (20) made on a chip based on semiconductors. The shared memory comprises: an integer number m, greater than one, of data buses (24); m address and control buses (200); m input/output interfaces (PI/PO, PO?), each input/output interface (PI/PO, PO?) being connected to one of the m data buses (24) and to one of the m address and control buses (200); an integer number p, greater than one, of memory banks (21, 22, 23), each memory bank (21, 22, 23) comprising: a memory (210, 220, 230), comprising a data input/output (I/O) and an address and control input (I) controlled by each of the address and control buses (200); a block of m switches (214, 224, 234), each of the m switches (214, 224, 234) being connected on the one hand to a memory data bus (213, 223, 233), said memory data bus (213, 223, 233) being connected to the data input/output (I/O) of the memory (210, 220, 230), and on the other hand to one of the m data buses (24).

Abstract: The present invention relates to a quick response power supply switching device. It also relates to a power supply network equipped with such a switch. The electrical power supply is connected to a set of blocks, the device comprises at least one switch (3) connecting the power supply (VDD) and the block (1), the value of the power supply current passing through the switch being controlled according to the difference between the power supply voltage (VDD) at the level of the other blocks and voltage threshold. The invention applies notably to all integrated circuits of recent technology in which it is important to reduce the leakage currents of the transistors in the unused circuit parts. The invention thus applies particularly to most systems powered by cell or battery and more particularly to portable telephone circuits.

Abstract: A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing storage of a page of words, each word of the page being identified by an address organized according to a hierarchical division defined by (@MSB, row address, column address), with @MSB identifying a particular module among the n modules. The circuit comprises first and second address buses, and first and second data buses used for reading and writing the modules, respectively. For each memory module, there is provided a multiplexer having two inputs connected to both address buses. The multiplexer output is connected to a row decoder and to first and second column decoders corresponding to the first and second data buses. Each multiplexer is controlled to allow writing and simultaneous reading of two distinct modules.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N?1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N?1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.

Abstract: A dynamic random access memory circuit including a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of the memory plane corresponding to a page of words. Two buffer registers are coupled with the memory plane for reading words in a page of the memory and for writing new words to a page of the memory, and the registers are used alternatively to access this memory plane. The buffer registers are dual-port memories and, moreover, the memory has an error correcting circuit allowing read-modify-write cycles applied to a group of n words within the same page. Whereby the reliability of the memory circuit is substantially increased and, moreover, an alternative solution to burn-in can even be offered. The invention also provides a method for controlling a dynamic memory having an error correcting code mechanism.

Abstract: A method is for refreshing a dynamic random access memory coupled to an error correction system, which uses an error correcting code. The dynamic random access memory includes groups of memory cells storing bits, each group of memory cells being subdivided into packets of memory cells. Each packet of memory cells is supplemented with the error correcting code. The method includes performing a retention test on each group of memory cells, and increasing a memory refresh frequency if a number of test groups of memory cells having at least one erroneous packet is greater than a threshold.

Abstract: A dynamic random access memory may include at least one group of memory cells, and a respective auxiliary memory for each group of memory cells. The respective auxiliary memory is for storing refresh information specific to each respective group of memory cells. The refresh information may include a current refresh period and a time remaining before refresh.

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N?1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N?1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.