Abstract: A dynamic memory includes a plurality of cells including capacitors connected by columns to bit lines and by rows to selection lines. An even row and an odd row contain reference cells, the cells of the other rows being memory cells. The capacitors of the reference cells have the same value as the capacitors of the memory cells. Means are also provided for, prior to reading a memory cell of an even row, connecting the selection line of the odd row of reference cells to an element having the same capacitance as a selection line, but which is precharged at the state opposite to the state of the selection line of the odd row of the reference cells.

Abstract: A bidimensional Finite Impulse Response (FIR) filter of rank 2p+1 for processing data associates a "vertical" filter and a "horizontal" filter. Each filter comprises 2p+1 cells and circuitry for vertically scanning the data according to stripes having a height of p data; circuitry for simultaneously providing on a first line a datum of a stripe, on a second line a datum of the former stride shifted by p data, and on a third line, a datum of the still former stripe again shifted by p data; and circuitry for, at each clock time, connecting each cell input to one of the three lines.

Abstract: A bidimensional Finite Impulse Response (FIR) filter of rank 2p+1 for processing data associates a "vertical" filter and a "horizontal" filter. Each filter includes 2p+1 cells and circuitry for vertically scanning the data according to stripes having a height of p data; circuitry for simultaneously providing on a first line a datum of a stripe, on a second line a datum of the former stripe shifted by p data, and on a third line, a datum of the still former stripe again shifted by p data; and circuitry for, at each clock time, connecting each cell input to one of the three lines.

Abstract: A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current source (M9, M10, M11) enabled by a selection input (Sij) of the crosspoint. The outputs of the first differential amplifier are connected to a second differential amplifier (M1, M2) fed by a second current source (I) common to all the crosspoints of a same column. The outputs of the second differential amplifier are connected to the pair of conductors (Oj1, Oj2) of an output column, an extremity of this column being connected to the high voltage source (Vdd) through a resistor (R).