Patents by Inventor Michele DERAI

Michele DERAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152289
    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi, Michele Derai
  • Publication number: 20210305203
    Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giovanni GRAZIOSI, Michele DERAI
  • Patent number: 11133242
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: September 28, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Michele Derai, Federico Giovanni Ziglioli
  • Publication number: 20210187663
    Abstract: A semiconductor substrate such as a semiconductor wafer includes a cutting line having a length. The semiconductor substrate is cut along the line by first selectively applying laser beam ablation energy to the semiconductor substrate a certain locations along the cutting line and then blade sawing along cutting line. The semiconductor substrate thus includes one or more ablated regions as well as one or more unablated regions at the cutting line.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonio BELLIZZI, Michele DERAI
  • Publication number: 20210183748
    Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 17, 2021
    Inventors: Michele DERAI, Dario VITELLO
  • Publication number: 20210183752
    Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 17, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Roberto TIZIANI
  • Publication number: 20210050226
    Abstract: Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Giovanni GRAZIOSI
  • Publication number: 20210050299
    Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 18, 2021
    Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Michele DERAI, Pierangelo MAGNI
  • Publication number: 20210013134
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Application
    Filed: September 9, 2020
    Publication date: January 14, 2021
    Inventors: Michele DERAI, Federico Giovanni ZIGLIOLI
  • Patent number: 10818578
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 27, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Michele Derai, Federico Giovanni Ziglioli
  • Publication number: 20190348350
    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 14, 2019
    Inventors: Fulvio Vittorio FONTANA, Giovanni GRAZIOSI, Michele DERAI
  • Publication number: 20190115287
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 18, 2019
    Inventors: Michele DERAI, Federico Giovanni ZIGLIOLI