Patents by Inventor Michele DERAI

Michele DERAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901250
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 13, 2024
    Assignee: STMicroelectron S.r.l.
    Inventors: Pierangelo Magni, Michele Derai
  • Publication number: 20240038650
    Abstract: Semiconductor devices of the type currently referred to as a System in a Package (SiP) and having embedded therein a transformer are produced by embedding at least one semiconductor chip in an insulating encapsulation at a first portion thereof. Over a second portion thereof at least partly non-overlapping with the first portion, a stacked structure is formed including multiple layers of electrically insulating material as well as respective patterns of electrically conductive material. The respective patterns of electrically conductive material have: a planar coil geometry for providing electrically conductive coils such as the windings of a transformer and a geometrical distribution providing electrically conductive connections to one or more semiconductor chips.
    Type: Application
    Filed: July 19, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Damian HALICKI, Michele DERAI
  • Patent number: 11887959
    Abstract: A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Guendalina Catalano
  • Publication number: 20230411258
    Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Roberto TIZIANI
  • Publication number: 20230402349
    Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 14, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Dario VITELLO
  • Publication number: 20230386980
    Abstract: A semiconductor die is attached on a die-attachment portion of a substrate such as a leadframe. The semiconductor die has a front surface opposite the substrate and one or more contact pads at the front surface having an outer surface finishing of a first electrically conductive material such as NiPd or Al. An encapsulation of laser direct structuring, LDS material is molded onto the semiconductor die attached on the substrate. Laser beam energy is applied to selected locations of the front surface of the encapsulation of LDS material to activate the LDS material at the selected locations and structure therein electrically conductive formations comprising one or more vias towards the contact pad. The vias comprise a second electrically conductive material that is different from the first electrically conductive material of the outer surface finishing of the contact pad.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 30, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Michele DERAI, Guendalina CATALANO
  • Patent number: 11749588
    Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 5, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Roberto Tiziani
  • Patent number: 11721614
    Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 8, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Dario Vitello
  • Publication number: 20230143539
    Abstract: A semiconductor die is arranged on a substrate and an encapsulation of laser direct structuring (LDS) material is molded onto the semiconductor die. A through mold via (TMV) extends through the encapsulation. This TMV includes a collar section that extends through a first portion of the encapsulation from an outer surface to an intermediate level of the encapsulation, and a frusto-conical section that extends from a bottom of the collar section through a second portion of the encapsulation. The collar section has a first cross-sectional area at the intermediate level. The first end of the frusto-conical section has a second cross-section area at the intermediate level. The second cross-sectional area is smaller than the first cross-sectional area. The TMV can have an aspect ratio which is not limited to 1:1.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 11, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Pierangelo MAGNI
  • Patent number: 11626355
    Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 11, 2023
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi, Michele Derai
  • Publication number: 20230035445
    Abstract: An encapsulation of laser direct structuring (LDS) material is molded onto first and second semiconductor dice. A die-to-die coupling formation between the first and second semiconductor dice includes die vias extending through the LDS material to reach the first and second semiconductor dice and a die-to-die line extending at a surface of the encapsulation between the die vias. After laser activating and structuring selected locations of the surface of the encapsulation for the die vias and die-to-die line, the locations are placed into contact with an electrode that provides an electrically conductive path. Metal material is electrolytically grown onto the locations of the encapsulation by exposure to an electrolyte carrying metal cations. The metal cations are reduced to metal material via a current flowing through the electrically conductive path provided via the electrode. The electrode is then disengaged from contact with the locations having metal material electrolytically grown thereon.
    Type: Application
    Filed: July 25, 2022
    Publication date: February 2, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Dario VITELLO, Michele DERAI
  • Patent number: 11552024
    Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Michele Derai, Pierangelo Magni
  • Publication number: 20230005803
    Abstract: A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.
    Type: Application
    Filed: June 23, 2022
    Publication date: January 5, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Giovanni GRAZIOSI, Michele DERAI
  • Patent number: 11521861
    Abstract: Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: December 6, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Giovanni Graziosi
  • Publication number: 20220238473
    Abstract: A semiconductor chip includes an electrical contact layer covered by a passivation layer. The semiconductor chip is encapsulated in an encapsulation formed by laser-direct-structuring (LDS) material. Laser beam energy is applied to the encapsulation to structure therein a through via passing through the encapsulation and removing the passivation layer at a bonding site of the electrical contact layer of the at least one semiconductor chip. The through via structured in the encapsulation is made electrically conductive so that the electrically-conductive through via is electrically coupled to, optionally in direct contact with, the electrical contact layer at a bonding site where the passivation layer has been removed.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 28, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Dario VITELLO, Michele DERAI
  • Publication number: 20220199424
    Abstract: A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fulvio Vittorio FONTANA, Michele DERAI
  • Publication number: 20220199564
    Abstract: A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Guendalina CATALANO
  • Publication number: 20220199477
    Abstract: A method of manufacturing semiconductor devices, such as QFN/BGA flip-chip type packages, arranging on a leadframe one or more semiconductor chips or dice having a first side facing towards the leadframe and electrically coupled therewith and a second side facing away from the leadframe. The method also includes molding an encapsulation on the semiconductor chip(s) arranged on the leadframe, where the encapsulation has an outer surface opposite the leadframe and comprises laser direct structuring (LDS) material. Laser direct structuring processing is applied to the LDS material of the encapsulation to provide metal vias between the outer surface of the encapsulation and the second side of the semiconductor chip(s) and as well as a metal pad at the outer surface of the encapsulation.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele DERAI, Dario VITELLO
  • Publication number: 20220068741
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pierangelo MAGNI, Michele DERAI
  • Publication number: 20210407894
    Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio FONTANA, Giovanni GRAZIOSI, Michele DERAI