Patents by Inventor Michele M. Franceschini

Michele M. Franceschini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9703858
    Abstract: According to an aspect, storing and querying conceptual indices (CIs) includes creating a conceptual inverted index (CII) from the CIs. The CII includes CII entries, each of which corresponds to a concept in a concept graph. Creating the CII includes populating each entry with pointers to documents selected from the CIs having likelihoods of being related to the concept that are greater than a threshold value, and the corresponding likelihoods. An aspect also includes receiving a query that includes a concept in the concept graph, and generating query results from a search that include at least a subset of the pointers to documents. Each of the CIs is associated with a corresponding document and includes a CI entry for each concept in the concept graph, and each of the CI entries specifies a value indicating a likelihood that the document is related to the concept in the concept graph.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Luis A. Lastras-Montano, Livio B. Soares, Mark N. Wegman
  • Publication number: 20170177714
    Abstract: According to an aspect, automatically adding new concepts to a concept graph includes receiving a string of text, searching a corpus of data to locate additional text related to the string of text, and extracting concepts from the additional text. The extracted concepts include a subset of concepts in the concept graph. The adding new concepts also includes determining whether the string of text should be linked to an existing concept in the concept graph, performing the linking based on determining that the string of text should be linked to the existing concept in the concept graph and, based on determining that the string of text should not be linked to an existing concept in the concept graph, adding a new concept to the concept graph. The new concept is associated with the string of text.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Michele M. Franceschini, Luis A. Lastras-Montano, Livio B. Soares, Mark N. Wegman
  • Publication number: 20170161279
    Abstract: A method and apparatus are provided for recommending concepts from a first concept set in response to user selection of a first concept Ci by performing a natural language processing (NLP) analysis comparison of vector representations of user concepts contained in written content authored by the user and candidate concepts in a first concept set to determine a similarity measure for each candidate concept, and to select therefrom one or more of the candidate concepts for display as recommended concepts which are related to the user concepts contained in written content authored by the user based on the similarity measure between each candidate concept and each user concept.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 8, 2017
    Inventors: Michele M. Franceschini, Tin Kam Ho, Luis A. Lastras-Montano, Oded Shmueli, Livio Soares
  • Publication number: 20170161619
    Abstract: A method and apparatus are provided for recommending concepts from a first concept set in response to user selection of a first concept Ci by performing a natural language processing (NLP) analysis comparison of the vector representations of a first concept set of candidate concepts and a second concept set of user-explored concepts to determine a similarity measure corresponding to each candidate concept, and to select therefrom one or more of the candidate concepts for display as recommended concepts which are related to the one or more user-explored concepts from the navigation history for the user based on the similarity measure for each candidate concept.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 8, 2017
    Inventors: Michele M. Franceschini, Tin Kam Ho, Luis A. Lastras-Montano, Oded Shmueli, Livio Soares
  • Publication number: 20170147287
    Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares
  • Publication number: 20170090992
    Abstract: A system and method dynamically provisions resources in a virtual environment. A current resource requirement is determined based on a current workload demand using one or more computer systems providing resources and access to the resources. The method and system includes comparing the current resource requirement with a current resource allocation using an engine communicating with resources. The engine is configured to allocate the resources, and the engine determines the resource requirement responsive to communications with a plurality of library instances. The library exposes a single-node interface for use by a user-application. The current resource allocation is modified based on the comparison of the current resource requirement with the current resource allocation, and in response to the current resource requirement, using the engine.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventors: John A. Bivens, Michele M. Franceschini, Ashish Jagmohan, Valentina Salapura
  • Patent number: 9606934
    Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares
  • Publication number: 20170075592
    Abstract: A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Patent number: 9576023
    Abstract: According to an aspect, summarizing relevance of a document to a conceptual query includes receiving the conceptual query, accessing concepts extracted from the document, and computing a degree to which the conceptual query is related to each of the extracted concepts. The computing is responsive to a metric that measures a relevance between the concepts in the conceptual query and the extracted concepts. An aspect also includes creating a summary by selecting a threshold number of the concepts having a greatest degree of relation to the conceptual query, and outputting the summary including the selected threshold number of concepts.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Luis A. Lastras-Montano, Livio B. Soares, Mark N. Wegman
  • Patent number: 9569109
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. Debrosse, Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge
  • Publication number: 20170017396
    Abstract: A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 19, 2017
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Patent number: 9542503
    Abstract: Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Livio Soares
  • Patent number: 9496018
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John K. Debrosse, Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge
  • Patent number: 9483580
    Abstract: Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Livio Soares
  • Publication number: 20160299975
    Abstract: Mechanisms, in a system comprising a host system and at least one accelerator device, for performing a concept analysis operation are provided. The host system extracts a set of one or more concepts from an information source and provides the set of one or more concepts to the accelerator device. The host system also provides at least one matrix representation data structure representing a graph of concepts and relationships between concepts in a corpus. The accelerator device executes the concept analysis operation internal to the accelerator device to generate an output vector identifying concepts in the corpus, identified in the at least one matrix representation data structure, related to the set of one or more concepts extracted from the information source. The accelerator device outputs the output vector to the host system which utilizes the output vector to respond to a request submitted to the host system associated with the information source.
    Type: Application
    Filed: April 9, 2015
    Publication date: October 13, 2016
    Inventors: Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares
  • Publication number: 20160291870
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 6, 2016
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Publication number: 20160293241
    Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: JOHN K. DEBROSSE, BLAKE G. FITCH, MICHELE M. FRANCESCHINI, TODD E. TAKKEN, DANIEL C. WORLEDGE
  • Publication number: 20160259826
    Abstract: Mechanisms are provided for performing a matrix operation. A processor is configured to perform hybrid compressed representation matrix operations on an input matrix that comprises zero value and non-zero value entries. A first compressed representation data structure corresponding to the input matrix, and a second compressed representation data structure are obtained, each utilizing a different format for representing the non-zero value entries of the input matrix. A matrix operation is iteratively executed on the input matrix using the first compressed representation data structure and the second compressed representation data structure. The first compressed representation data structure is utilized for a first subset of iterations of the matrix operation and the second compressed representation data structure is utilized for a second subset of iterations of the matrix operation different from the first subset of iterations.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 8, 2016
    Inventors: Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Haifeng Qian, Livio B. Soares
  • Publication number: 20160224473
    Abstract: Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of an input matrix. An input matrix, which comprises nodes associated with elements of the matrix, is received. The nodes are clustered into clusters based on numbers of connections with other nodes within and between the clusters, and the clusters are ordered by minimizing a total length of cross cluster connections between nodes of the clusters, to thereby generate a reordered matrix. A lookup table is generated identifying new locations of nodes of the input matrix, in the reordered matrix. A matrix operation is then performed based on the reordered matrix and the lookup table.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares
  • Patent number: 9342448
    Abstract: A queued, byte addressed system and method for accessing flash memory and other non-volatile storage class memory, and potentially other types of non-volatile memory (NVM) storage systems. In a host device, e.g., a standalone or networked computer, having attached NVM device storage integrated into a switching fabric wherein the NVM device appears as an industry standard OFED™ RDMA verbs provider. The verbs provider enables communicating with a ‘local storage peer’ using the existing OpenFabrics RDMA host functionality. User applications issue RDMA Read/Write directives to the ‘local peer (seen as a persistent storage) in NVM enabling NVM memory access at byte granularity. The queued, byte addressed system and method provides for Zero copy NVM access. The methods enables operations that establish application private Queue Pairs to provide asynchronous NVM memory access operations at byte level granularity.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 17, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Blake G. Fitch, Michele M. Franceschini, Lars Schneidenbach, Bernard Metzler