Abstract: A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator.

Abstract: A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.

Abstract: A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.

Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Abstract: An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

Abstract: A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.

Abstract: A touchscreen resistive sensor includes a network of resistive sensor branches coupled to a number of sensor nodes arranged at touch locations of the touchscreen. A test sequence is performed by sequentially applying to each sensor node a reference voltage level, jointly coupling to a common line the other nodes, sensing a voltage value at the common line, and declaring a short circuit condition as a result of the voltage value sensed at the common line reaching a short circuit threshold. A current value level flowing at the sensor node to which the reference voltage level is applied is sensed and a malfunction of the resistive sensor branch coupled with the sensor node to which a reference voltage level is applied is generated as a result of the current value sensed at the sensor node reaching an upper threshold or lower threshold.

Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.

Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.

Abstract: A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.

Abstract: A thermographic sensor is proposed. The thermographic sensor includes one or more thermo-couples, each for providing a sensing voltage depending on a difference between a temperature of a hot joint and a temperature of a cold joint of the thermo-couple; the thermographic sensor further comprises one or more sensing transistors, each driven according to the sensing voltages of one or more corresponding thermo-couples for providing a sensing electrical signal depending on its temperature and on the corresponding sensing voltages. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.

Abstract: An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

Abstract: Radiation sensor including a detection assembly and a chopper assembly, which are mechanically coupled to delimit a main cavity; and wherein the chopper assembly includes: a suspended movable structure, which extends in the main cavity; and an actuation structure, which is electrically controllable to cause a change of position of the suspended movable structure. The detection unit includes a detection structure, which faces the main cavity and includes a number of detection devices. The suspended movable structure includes a first shield of conductive material, which shields the detection devices from the radiation, the shielding of the detection devices being a function of the position of the suspended movable structure.

Abstract: An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.

Abstract: A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.

Abstract: An embodiment converter circuit comprises an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path which comprises a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word which is a function a correction value of the offset in the analog input signal.

Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.

Abstract: A method of sensing a temperature includes providing a voltage to reverse bias a PN junction of a junction diode. The PN junction has a junction capacitance. The method includes providing a reverse bias voltage change across the PN junction and detecting a value of the junction capacitance in response to the reverse bias voltage change. The value of the junction capacitance is a function of a temperature of the PN junction. An output signal is generated based on the detected junction capacitance, where the output signal indicates a temperature of an environment containing the junction diode.