Abstract: An IGBT module comprises a ceramic substrate having a collector wiring element on a surface thereof, an IGBT chip provided on the collector wiring element, an insulative member provided on the collector wiring element and configured to cover at least edge portions of the IGBT chip, and an insulative sealing resin, provided on the ceramic substrate, for covering the IGBT chip and the insulative member. The sealing resin has lower insulation properties than the insulative member.

Abstract: A semiconductor device includes an active region with a main semiconductor device section, and a junction-termination region therearound. A first diffusion layer of a second conductivity type is formed in a surface of a first semiconductor layer of a first conductivity type, and extends from the active region into the junction-termination region. A second diffusion layer of the second conductivity type is formed in contact with the first diffusion layer, and extends in the junction-termination region. A first contact electrode is disposed in the active region and in contact with the first diffusion layer, and electrically connected to a first main electrode of the main semiconductor device section. A second contact electrode is disposed in the junction-termination region and in contact with the first diffusion layer, and surrounds the active region. A connection electrode electrically connects the first and second contact electrodes to each other.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: Provided a pressure-contact type semiconductor device including: a plurality of semiconductor chips; a heat buffer plate provided on one surface side of the plural semiconductor chips; and a metal electrode plate provided on the heat buffer plate on a side opposite the plural semiconductor chips, a surface thereof at any position not facing the plural semiconductor chips on the heat buffer plate side having a region which alleviates elastic deformation of the heat buffer plate. Also provided is a pressure-contact type semiconductor device including: a plurality of semiconductor chips; a heat buffer plate provided on one surface side of the plural semiconductor chips; and a metal electrode plate provided on the heat buffer plate on a side opposite the plural semiconductor chips, a peripheral shape thereof extending beyond and thus being larger than a peripheral shape of the heat buffer plate.

Abstract: A semiconductor device includes an active region with a main semiconductor device section, and a junction-termination region therearound. A first diffusion layer of a second conductivity type is formed in a surface of a first semiconductor layer of a first conductivity type, and extends from the active region into the junction-termination region. A second diffusion layer of the second conductivity type is formed in contact with the first diffusion layer, and extends in the junction-termination region. A first contact electrode is disposed in the active region and in contact with the first diffusion layer, and electrically connected to a first main electrode of the main semiconductor device section. A second contact electrode is disposed in the junction-termination region and in contact with the first diffusion layer, and surrounds the active region. A connection electrode electrically connects the first and second contact electrodes to each other.

Abstract: An IGBT module comprises a ceramic substrate having a collector wiring element on a surface thereof, an IGBT chip provided on the collector wiring element, an insulative member provided on the collector wiring element and configured to cover at least edge portions of the IGBT chip, and an insulative sealing resin, provided on the ceramic substrate, for covering the IGBT chip and the insulative member. The sealing resin has lower insulation properties than the insulative member.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance.

Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).

Abstract: A multichip press-contact type semiconductor device including a plurality of semiconductor chips, a plurality of heat buffer plates, a conductive metal sheet, and first and second press-contact electrode plates. The heat buffer plates are disposed to correspond to the plurality of semiconductor chips. The conductive metal sheet is located on the plurality of heat buffer plates and substantially decreases the parasitic inductance by causing a short-circuit in electrode wiring connecting the semiconductor chips. The first press-contact electrode plate is located on the conductive metal sheet, and has column protrusions corresponding to the semiconductor chips on the surface facing the semiconductor chips. The second press-contact electrode plate is located on the side of the rear surface of the semiconductor chips. The first and second press-contact electrode plates hold therebetween the conductive metal sheet, the heat buffer plates, and the semiconductor chips, piled on each other.

Abstract: A pressure-contact type semiconductor device such as an insulated gate bipolar transistor. The device includes semiconductor chip, a gate electrode on a first surface of the semiconductor chip, an emitter electrode insulated and separated from the gate electrode, and an emitter sensing electrode on the first surface of the semiconductor chip. A collector layer is on the second surface of the semiconductor chip. The emitter sensing electrode monitors the emitter voltage. Because the emitter sensing electrode is on the semiconductor chip, the emitter sensing electrode is not influenced by inductance between an emitter and an emitter terminal.

Abstract: In the present invention, by virtue of heat buffer plates respectively located on the major surfaces of IGBT chips and FRD chips arranged in a single plane, the total thickness of each chip and a corresponding one of the heat can be set to a substantially predetermined value. A thickness-correcting member having elongated projections corresponding to the chips is provided on those surfaces of the heat buffer plates which is remote from the chips. A heat buffer disk plate is provided on those surfaces of the chips which are opposite to the major surfaces thereof. The thickness-correcting member, the heat buffer plates and the IGBT and FRD chips are held and simultaneously pressed between an emitter press-contact electrode plate and a collector press-contact electrode plate.

Abstract: A reverse conducting gate-turnoff thyristor includes a switching device section, a diode section, and an isolating section located between the switching device section and the diode section. The isolating section includes an impurity layer formed by controlling impurity diffusion and having an impurity concentration lower than those of the switching device section and the diode section.

Abstract: The top-side (n-type) electrode and bottom-side (p-type) electrode of a Si chip with a p-n junction are pressed against a Cu cathode electrode and a Cu anode electrode via Mo plates respectively, thereby establishing electrical connection. The inner wall of a case is round and the Si chip is almost square. The top of the case is covered with ceramic, for example. A washer is a compression member. A chip frame holds the Si chip and Mo plates in compression positions and simultaneously determines their locations within the case. Specifically, the side face of the Si chip is not flush with the side face of each of the Mo plates. This enables the chip frame to make the creepage distance longer. Since the chip frame is a single chip frame without any joint, the creepage distance between the anode and cathode electrodes is defined by part of the chip frame that faces part of the surface of the Si chip and parts of the surfaces of the Mo plates sandwiching the Si chip between them.

Abstract: IGBT chips and FRD chips are arranged on the same plane so as to be press-contacted by an emitter press-contact electrode plate and a collector press-contact electrode plate at the same time. The FRD chips are arranged at a central portion, and the IGBT chips are arranged at the peripheral portion of the FRD chips. A resin substrate having an opening in its contact portion between a main surface of each of said chip and the emitter press-contact electrode plate is provided between both press-contact electrode plates. Gate press-contact electrodes are formed on the resin substrate to be electrically connected to a gate electrode of each of the IGBT chips. Also, gate wires are fixed to the resin substrate to supply a control signal for controlling the IGBT chips to the gate electrode of the IGBT chips from the gate wires through the gate press-contact electrode.

Abstract: A press-contact type semiconductor device having multiple semiconductor substrates, a periphery of which being enclosed by a chip frame of insulating resin a first electrode plate and a second electrode plate. The semiconductor substrates are arranged on a plane so as to abut against the chip frame. The semiconductor substrates are press-contacted from the upper and the lower sides by the first electrode plate and the second electrode plate.

Abstract: In a semiconductor device, a pellet electrode, which is formed on a mesa-shaped pellet, and an external electrode, with which a package is provided, are in pressure-contact with each other. A soft-metal plate which has projections along its surface is arranged between the external electrode and the pellet electrode.

Abstract: A crimp-type semiconductor device is provided with a semiconductor substrate having a lifetime-controlled region. This lifetime-controlled region is in the form of a ring, and the lifetime of the minority carriers is shortened in the region. Second-conductivity type impurity regions, which serve as emitter layers, are formed on the semiconductor substrate such that they provide a plurality of concentric arrays. The inner diameter of the ring-like lifetime-controlled region is longer than the diameter of an enveloping circle which is obtained by connecting the radially-inner ends of the impurity regions of the outermost array.

Abstract: A gate turn-off thyristor of the crimp and anode shortcircuit type includes a semiconductor pellet having anode, cathode and gate electrodes formed on each of first and second main surfaces thereof, with the gate electrode entering into the cathode electrodes. First and second electrode members are positioned sandwiching the semiconductor pellet between them and opposing to the electrodes. First and second electrode posts are positioned sandwiching the semiconductor pellet and the electrode members between them and opposing to the electrode members. Those faces of the electrodes, electrode members and electrode posts which are opposed to one another are not fixed but contact-pressed to one another. The semiconductor pellet has at the outer rim portion thereof a region where no current flows. The outer rim of each of the electrode member and post terminates on the region through which no current flows.