Patents by Inventor Michihiro Murata

Michihiro Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9904170
    Abstract: When a reticle is first used, the reticle is loaded in a projection exposure device and measured by either oblique measurement or random measurement, thereby avoiding the fear of uneven sampling and determining the reticle transmittance of the entire reticle as the parent population, without increasing the sampling count. The same effect can be obtained by making the measurement spot size, which is fixed in general, variable and by changing the angle of incidence in relation to the measurement spot size.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 27, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Michihiro Murata, Yutaka Gomi
  • Publication number: 20170351180
    Abstract: When a reticle is first used, the reticle is loaded in a projection exposure device and measured by either oblique measurement or random measurement, thereby avoiding the fear of uneven sampling and determining the reticle transmittance of the entire reticle as the parent population, without increasing the sampling count. The same effect can be obtained by making the measurement spot size, which is fixed in general, variable and by changing the angle of incidence in relation to the measurement spot size.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 7, 2017
    Inventors: Michihiro MURATA, Yutaka GOMI
  • Patent number: 9733567
    Abstract: When a reticle is first used, the reticle is loaded in a projection exposure device and measured by either oblique measurement and random measurement, thereby avoiding the fear of uneven sampling and determining the reticle transmittance of the entire reticle as the parent population, without increasing the sampling count. The same effect can be obtained by making the measurement spot size, which is fixed in general, variable and by changing the angle of incidence in relation to the measurement spot size.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 15, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Michihiro Murata, Yutaka Gomi
  • Publication number: 20160091391
    Abstract: When a reticle is used first, the reticle is actually loaded in a projection exposure device and measured by one of oblique measurement and random measurement, thereby avoiding the fear of uneven sampling and determining the reticle transmittance of the entire reticle as the parent population, without increasing the, sampling count. The same effect can be obtained by making the measurement spot size, which is fixed in general, variable and by changing the angle of incidence in relation to the measurement spot size.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 31, 2016
    Inventors: Michihiro MURATA, Yutaka GOMI
  • Patent number: 8482401
    Abstract: A safety belt includes a connecting member including a rope, an attaching portion connected to a first end of the rope and arranged to be attached to a body belt worn around a body of a worker, a hook connected to a second end of the rope, and a load detection portion arranged to detect whether or not a load is applied to the connecting member and to output a load detection signal. The safety belt also includes a control device that includes a receiver unit arranged to receive the load detection signal, a control unit arranged to determine a status of the worker or a status of the safety belt based on the load detection signal, and a notification unit arranged to provide a notification in accordance with control by the control unit corresponding to the determined status.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: July 9, 2013
    Assignees: Techno Links International, Inc., Fujii Denko Co., Ltd.
    Inventors: Osamu Morino, Akitomo Kozuki, Michihiro Murata
  • Patent number: 8119312
    Abstract: In a manufacturing method for divisionally exposing a wafer, a focus correction processing is performed after a shot is moved to a position where the focus correction processing for all foci is enabled when the shot is at a wafer outer periphery, and a portion overlapped with an adjacent exposure area is shielded from light by a reticle blind to expose only an opening area unshielded by the reticle blind.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 21, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Michihiro Murata
  • Patent number: 7981804
    Abstract: A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: July 19, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Michihiro Murata
  • Publication number: 20110090079
    Abstract: A safety belt includes a connecting member including a rope, an attaching portion connected to a first end of the rope and arranged to be attached to a body belt worn around a body of a worker, a hook connected to a second end of the rope, and a load detection portion arranged to detect whether or not a load is applied to the connecting member and to output a load detection signal. The safety belt also includes a control device that includes a receiver unit arranged to receive the load detection signal, a control unit arranged to determine a status of the worker or a status of the safety belt based on the load detection signal, and a notification unit arranged to provide a notification in accordance with control by the control unit corresponding to the determined status.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 21, 2011
    Applicants: FUJII DENKO CO., LTD., TECHNO LINKS INTERNATIONAL, INC.
    Inventors: Osamu MORINO, Akitomo KOZUKI, Michihiro MURATA
  • Publication number: 20100203433
    Abstract: In a manufacturing method for divisionally exposing a wafer, a focus correction processing is performed after a shot is moved to a position where the focus correction processing for all foci is enabled when the shot is at a wafer outer periphery, and a portion overlapped with an adjacent exposure area is shielded from light by a reticle blind to expose only an opening area unshielded by the reticle blind.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 12, 2010
    Inventor: Michihiro Murata
  • Publication number: 20090203210
    Abstract: A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 13, 2009
    Applicant: Seiko Instruments Inc.
    Inventor: Michihiro Murata
  • Patent number: 6407904
    Abstract: A multi-layer capacitor is constructed to minimize equivalent series inductance, increase resonance frequency, reduce the size of the capacitor and greatly improve the ease of mounting of the capacitor. A dimension in a length direction and a dimension in a width direction of a capacitor body are substantially equal, and a pattern of opposing first and second internal electrodes is substantially square. First lead-out portions of the first internal electrode and second lead-out portions of the second internal electrode are extended onto two side surfaces and two end surfaces. First external electrode terminals connected to the first lead-out portions and second external electrode terminals connected to the second lead-out portions are arranged so that they alternate adjacently and are arranged such that oppositely disposed external electrode terminals have opposite polarities.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: June 18, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Yasuyuki Naito, Masaaki Taniguchi, Haruo Hori, Takanori Kondo, Michihiro Murata, Yoshitaka Tanino
  • Patent number: 6327134
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: December 4, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo, Michihiro Murata
  • Patent number: 6292350
    Abstract: A multi-layer capacitor including a capacitor body having four sides including a first pair of opposed sides and a second pair of opposed sides, the capacitor body including a plurality of dielectric layers and at least a pair of first and second internal electrodes that oppose each other via one of the dielectric layers, the first internal electrode having first lead-out portions, the second internal electrode having second lead-out portions, the first and second lead-out portions being arranged to interdigitate with each other. The first polarity external electrode terminals are electrically connected to the first lead-out portions. At least one of the first polarity external electrode terminals is arranged on each of the first pair of opposed sides and at least one of the first polarity external electrode terminals being arranged on each of the second pair of opposed sides of the capacitor body. Second polarity external electrode terminals are electrically connected to the second lead-out portions.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: September 18, 2001
    Assignee: Murata Manufacturing, Co., LTD
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoiohi Kuroda, Takanori Kondo, Michihiro Murata, Yoshitaka Tanino
  • Patent number: 6266229
    Abstract: A multi-layer capacitor device includes a capacitor body including first electrode plates and a plurality of second electrode plates. The first and second electrode plates are interleaved with each other in opposed and spaced apart relation. A dielectric material is located between each opposed set of the first and second electrode plates. The first and second electrode plates each include a main electrode portion and a plurality of spaced apart lead structures extending therefrom. Respective lead structures of the first electrodes plates are located adjacent respective lead structures of the second electrode plates in an interdigitated arrangement. A plurality of electrical terminals are located on each of the opposed side surfaces of the capacitor body. A plurality of first polarity electrical terminals and a plurality of second polarity electrical terminals, respectively, located on the capacitor body.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: July 24, 2001
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Takanori Kondo, Michihiro Murata, Yoshitaka Tanino
  • Patent number: 6266228
    Abstract: A multi-layer capacitor device includes a substantially rectangular capacitor body including first electrode plates and second electrode plates. and a dielectric material is located between each opposed set of the first and second electrode plates. The first and second electrode plates each includes a main electrode portion and a plurality of spaced apart lead structures extending therefrom, respective lead structures of the first electrodes plates being located adjacent respective lead structures of the second electrode plates in an interdigitated arrangement. A plurality of electrical terminals are located on the side surfaces of the substantially rectangular capacitor body. Each of the first polarity terminals is adjacent to one of the second polarity terminals and each of the second polarity terminals is adjacent to one of the first polarity terminals.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: July 24, 2001
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Takanori Kondo, Michihiro Murata, Yoshitaka Tanino
  • Patent number: 5344518
    Abstract: A pyroelectric IR-sensor in which a pyroelectric light receiving element is mounted on a MID substrate or a ceramic substrate having a thermal conductivity less than 0.02 cal/cm.sec..degree.C. Both ends of the pyroelectric light receiving element are supported by the substrate, with the central portion of the pyroelectric light receiving element being spaced from the substrate. Chip parts are mounted on the substrate.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: September 6, 1994
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoru Ito, Michihiro Murata, Norio Fukui, Keizou Yamamoto, Tetsujiro Sawao, Satoshi Awata, Yasuo Tada, Satoru Kawabata
  • Patent number: 5323025
    Abstract: A pyroelectric IR-sensor in which a pyroelectric light receiving element is mounted on a MID substrate or a ceramic substrate of which thermal conductivity is less than 0.02 cal/cm.sec..degree. C. in a manner that both end portions of the pyroelectric light receiving element are supported by the substrate with the central portion of the pyloelectric light receiving element being spaced from the substrate, and chip parts are further mounted on the substrate.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: June 21, 1994
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Satoru Ito, Michihiro Murata, Norio Fukui, Keizou Yamamoto, Tetsujiro Sawao, Satoshi Awata, Yasuo Tada, Satoru Kawabata
  • Patent number: 5270555
    Abstract: A pyroelectric IR-sensor in which a pyroelectric light receiving element is mounted on a MID substrate or a ceramic substrate having a thermal conductivity less than 0.02 cal/cm.multidot.sec.multidot..degree.C. Both ends of the pyroelectric light receiving element are supported by the substrate, with the central portion of the pyroelectric light receiving element being spaced from the substrate. Chip parts are mounted on the substrate.
    Type: Grant
    Filed: May 7, 1992
    Date of Patent: December 14, 1993
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoru Ito, Michihiro Murata, Norio Fukui, Keizou Yamamoto, Tetsujiro Sawao, Satoshi Awata, Yasuo Tada, Satoru Kawabata
  • Patent number: 5263370
    Abstract: A liquidometer composed of a siphon for emitting a sample liquid stored in a reservoir and a liquid level sensor for sensing the level of the sample remained in the reservoir. The siphon further includes a pair of sensors for counting the number of emission thereof, while the liquid level sensor includes two rows of resistive film with a plurality of sensing elements embedded therein. Outside the liquidometer, there are provided a counter connected to the emission sensor, a level calculator connected to the liquid level sensor, and a calculator coupled to both. A gross amount of the sample liquid having been measured for a period of hours is obtained by adding together a count signal from the counter which represents the quantity of the sample liquid fully stored in the reservoir and a signal from the level counter which represents the liquid level of the remaining sample liquid.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: November 23, 1993
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Michihiro Murata, Akira Kumada, Kenji Matsuo, Shigeo Yamazaki
  • Patent number: 5226313
    Abstract: A body fluid excretion volume measurement apparatus for medical application. The apparatus stores body fluid excreted from patients in a body fluid storage tank and measures the resistance value with a resistance sensor. The resistance value depends on the shape of the body fluid storage tank, and if the tank is columnar, the resistance value is monotonically increasing with respect to the depth of body fluid. The output of the resistance sensor is processed by a measurement part and electric measurement of the body fluid volume stored in the body fluid storage tank is performed automatically.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: July 13, 1993
    Assignees: Murata Mfg. Co., Ltd., Kobayashi Pharmaceutical Co., Ltd.
    Inventors: Michihiro Murata, Akira Kumada, Kenji Matsuo, Chitaka Ochiai, Shigeo Yamazaki, Masaaki Kimura, Naoyuki Kohriya