Abstract: An object is to provide a pen nib that can be used, for example, for a touch panel with writing feeling comparable to a conventional pen. The pen nib has a pen nib body that is formed of a bundle of fibers and is coated with a conductive material and made conductive.

Abstract: Elastic polyester fibers having a high anti-cohesive property (separability) include (A) a polyester elastomer and (B) 0.2 to 10%, based on the weight of the elastomer, of an anti-cohesive agent including (a) at least one alkali metal salt of organic sulfonic acid of the formula: R.sup.1 --S0.sub.3 M, wherein R.sup.1 =C.sub.5-25 hydrocarbon group, M=alkali metal, and (b) at least one compound of the formulae (2)-(6): R.sup.2 --X.sub.p --CH.sub.2 CH.sub.2 OH (2), R.sup.3 --COO--CH.sub.2 CH(OH)CH.sub.2 OH (3), R.sup.4 --COO--(CH.sub.2 CH.sub.2 O).sub.m --H (4), R.sup.5 --O--(CH.sub.2 CH.sub.2 O).sub.n H (5) and R.sup.6 --CONHCH.sub.2 CH.sub.2 NHCO--R.sup.7 (6), wherein R.sup.2 -R.sup.7 =C.sub.5-25 hydrocarbon group, X=--CONY or ##STR1## group, p=0 or 1, m, n=5 to 50.

Abstract: A mesomorphic compound represented by the following formula (I): ##STR1## wherein R.sub.1, R.sub.2 and R.sub.3 independently denote methyl group or a mesomorphic residual group, at least one of R.sub.1, R.sub.2 and R.sub.3 being a mesomorphic residual group having an optically active group of the formula below as a terminal flexible group: ##STR2## wherein R.sub.4 is an alkyl group having 1-12 carbon atoms; n is an integer of 0-10; m is an integer of 1-10; and L is an integer of 1-100. The mesomorphic compound is usable for constituting a liquid crystal composition and a liquid crystal device having a large picture area and capable of showing an improved switching characteristic and a good impact resistance.

Abstract: Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.

Abstract: Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.

Abstract: A sense.multidot.input/output gate includes MOS transistors which are provided for each bit line pair and have their gates and drains cross-coupled together, separating transistors arranged between the gates and the drains of the MOS transistors, and column selecting gates connecting the drains of the MOS transistors to internal data transmitting lines. The semiconductor memory device further includes a load circuit which precharges the internal data transmitting lines to a predetermined potential in a test mode, and a line test circuit which determines existence and nonexistence of a defective memory cell based on the potentials of the internal data transmitting lines. In the data reading operation, the column selecting gates become conductive while the separating transistors are in OFF state, and the potential of the internal data transmitting line changes by virtue of the discharge through one of the cross-coupled MOS transistors. In this construction, the sense amplifier is used also as the read gate.

Abstract: An input circuit of a semiconductor device includes a P type well formed on the main surface of a semiconductor substrate, and an N type region formed on the main surface in the P type well. A P-N junction is formed by the N type region and the P type well. An input voltage is applied to the N type region, which input voltage is applied to an internal circuit formed on the semiconductor substrate. When the P-N junction is rendered conductive by an application of an excessive voltage to the input voltage, the current caused by the excessive voltage is absorbed to the supply potential through the P type region formed in the P well.

Abstract: A semiconductor device having a trench (30) comprises a semiconductor substrate (11), a plurality of elements (13) provided on the semiconductor substrate, a trench (30) provided between the elements and an insulating material (12) embedded in the trench for isolating the elements. The trench has its bottom portion region enlarged in both sides.The semiconductor device is manufactured by enlarging the bottom portion region of the trench by etching.

Abstract: A clock generator circuit of a dynamic RAM comprises a power-on reset circuit and an NOR gate connected to a RAS terminal and the reset circuit. In operation, the powre-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level RAS signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic RAM at the time of turning on the power supply.

Abstract: A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a litle increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.

Abstract: A dynamic random access memory with a folded bit line structure (BLL.sub.j1, BLL.sub.j1, BLR.sub.j1 BLR.sub.j1), each pair of bit lines being divided into a plurality of blocks (MCB.sub.j1, MCB.sub.j2), comprises equalizing transistors (Q.sub.j9, Q.sub.j10) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q.sub.j9, Q.sub.j10) stop equalizing selectively and at different times among the blocks.

Abstract: An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 >R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3 <<R.sub.2.

Abstract: The present invention comprises a field oxide film formed on a silicon substrate, an underlying film of polycrystal silicon formed on a portion thereof and an insulating film formed so as to cover the field oxide film comprising the underlying film. A surface stepped portion of the insulating film is formed by a portion with an underlying film and a portion without an underlying film under the insulating film, and a blowout portion of a fuse is formed along the surface stepped portion. There are terminal portions at both ends of the blowout portion of the fuse and an aluminum line is connected thereto. In addition, the whole portions comprising the fuse portion are covered with another insulating film and the whole is protected. The fuse is employed as one example in a redundancy circuit of a MOS dynamic RAM having redundancy memory cells.

Abstract: An arbiter circuit is disclosed for processing requests made at least two subsystems in a multiprocessor system for access to a resource shared by the subsystems. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates. The flip-flop is operative in response to a time-staggered request signals from the subsystems to provide a request acknowledging signal to the shared resource. When two request signals are simultaneously supplied to the arbiter circuit, the outputs from the pair of NAND gates tend to stay at an intermediate level between the normal two distincitive logic levels, failing to produce an acknowledgment signal. However, the intermediate level of the NAND gate outputs is sensed by a NOR gate to a trigger a switching device into conduction, by means of which one of the intermediate NAND gate outputs is positively shifted to either of the active logic levels for the generation of an acknowledgement signal to the shared resources.

Abstract: A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level row address strobe (RAS) signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic random access memory (RAM) at the time of turning on the power supply.

Abstract: A resistor is connected to an input portion of a CMOS inverter. An input of the CMOS inverter is affected by a time constant of an RC circuit comprising the resistor and gate stray capacitance of the CMOS inverter. In addition, there is provided an n channel MOS transistor having a drain and a source connected to both ends of the resistor, respectively, and a gate connected to an input signal source. Only in the rising portion of an input signal, the n channel MOS transistor is turned on, so that the resistor is bypassed. Thus, a waveform of output of the CMOS inverter is not delayed at the falling portion. Only at the rising portion, the waveform thereof is delayed due to the time constant of the above described RC circuit.

Abstract: A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a little increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.

Abstract: A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.

Abstract: The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1.

Abstract: A plurality of RAM chips, a V.sub.CC power supply terminal and a V.sub.SS power supply terminal are all formed on one wafer. Each of the RAM chips comprises an MOS circuit comprising a V.sub.CC power supply line and a V.sub.SS power supply line, a power supply terminal and a ground terminal. The ground terminal is connected to the V.sub.SS power supply line through an N channel MOS transistor, and the power supply terminal is connected to the V.sub.CC power supply line. The MOS transistor has a gate connected to a power supply terminal through a fuse element. The power supply terminals and the ground terminals in the plurality of RAM chips are connected to the V.sub.CC power supply terminal and the V.sub.SS power supply terminal, respectively, by aluminum interconnections. When a power-supply voltage is applied between the V.sub.CC power supply terminal and the V.sub.