Abstract: A dynamic RAM having a plurality of pairs of folded bit lines each divided into a plurality of pairs of divided bit lines comprises transfer gates (QT1, QT2) provided for each pair of divided bit lines for connecting/disconnecting the pair of adjacent divided bit lines to each other, sense amplifiers (SA1, SA2) provided for each of the pairs of divided bit lines for detecting and amplifying potential difference between the pairs of divided bit lines, restore circuits (RE1, RE2) provided for each of the pairs of divided bit lines for boosting the potential on the bit line on the side of a high potential of the pairs of the divided bit lines, and a control circuit (TG) for turning the transfer gates (QT1, QT2) on after a predetermined time since the sense amplifier was operated in response to a sense amplifier activating signal.

Abstract: In a dynamic random access memory with a folded bit line structure, in which a memory cell array is divided into a plurality of blocks (CAL1, CAL2) and the bit lines (BL1, BL1, BL2, BL2) of the adjacent blocks (CAL1, CAL2) are connected to each other by using transfer gate transistors (QT1, QT2), sense amplifiers (SA1, SA2) and restore circuits (RE1, RE2) for detecting potential difference between pair of bit lines are provided for each of the pairs of bit lines (BL1, BL1, BL2, BL2) of each of the blocks (CAL1, CAL2), the transfer gate transistors (QT1, QT2) to turned on by being triggered by an activating signal to a restore circuit first operated, out of restore circuits connected to bit lines connected to the transfer gate transistor (QT1, QT2).

Abstract: An internal power supply voltage generator for generating an internal power supply voltage for a semiconductor integrated device includes first and second reference voltage generators which produce first and second reference voltages having respective values a predetermined amount above and below an optimal value of the internal power supply voltage. The first and second reference voltage generators are constructed of a pair of serially connected NMOS and PMOS transistors, respectively, which transistors are connected between an external voltage supply and ground. The first and second reference voltages are applied to a CMOS output stage constructed of a NMOS and PMOS transistor serially connected between the external voltage supply and ground, the gates of the transistors being coupled to the first and second reference voltages, so as to provide said internal power supply voltage at a common node between the transistors.

Abstract: A dynamic random access memory comprises N channel sense amplifiers, P channel sense amplifiers and an equalizing MOSFET each provided for each of bit line pairs. The N channel sense amplifiers and the P channel sense amplifiers are operated by sense amplifier driving signals. In each of the N channel sense amplifiers, an MOSFET is connected between one of bit lines and an interconnection for transmitting a sense amplifier driving signal. In addition, a precharge potential generating circuit for generating a potential of (1/2)V.sub.CC is connected to the interconnection for transmitting the sense amplifier driving signal through a MOSFET. The bit line pairs are equalized by the equalizing MOSFET. Then, in each of the N channel sense amplifiers, the above described interconnection and one of the bit lines are connected to each other, and the above described interconnection and the precharge potential generating circuit are connected to each other.

Abstract: A dynamic RAM comprises a sense amplifier and a restore circuit for each pair of divided bit lines. Sense operation can be performed in a fast and stable manner and the gate voltage of a transfer gate transistor need not be boosted over the power supply potential, so that the access time of the dynamic RAM can be reduced, operation margin thereof is increased, and reliability is improved.

Abstract: A decoder part is formed by a main decoder part C and a plurality of subdecoder parts D.sub.0 to D.sub.3 connected with the main decoder part C, and a plurality of such decoder parts are provided. In such structure, the main decoder part specifies one of a plurality of decoder parts and a CMOS circuit (PMOS transistor T.sub.0 and NMOS transistors T.sub.0 ', . . . , PMOS transistor and NMOS transistor T.sub.3 ') specifies one of the subdecoder parts and PMOS transistors (T.sub.00 to T.sub.03, . . . , T.sub.30 to T.sub.33) select finally decoded output.

Abstract: An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.

Abstract: A dynamic random access memory that contains a memory cell array including a plurality of memory cells includes a pre-amplifier intended to amplify data which is read out from a memory cell accessed by an address signal; a main-amplifier intended to amplify the output of the pre-amplifier and output the amplified signal; and a driver circuit intended to output a driving signal for driving the main-amplifier, the driver circuit includes a first and a second transistor, wherein a drain of the first transistor is connected to a node corresponding to an output terminal of the driver circuit, with a source of the first transistor being earthed and with a gate thereof being connected to the drain of the second transistor, and wherein a gate of the second transistor is connected to the node with a source thereof being earthed.

Abstract: The single input gate electrode in a conventional CCD shift register is replaced by four spaced electrodes. The fourth electrode adjacent to the first transfer electrode has an area larger than that of the second electrode which always has a DC voltage applied thereto. Three driving pulses are applied in a predetermined sequence to the first, third and fourth electrodes while the two bit values of 2-bit information are written into the register and a charge is accumulated directly under the fourth input gate electrode at one of four levels as determined by the combination of the write bit values. Then the accumulated charge is stepwise transferred in the same manner as in conventional CCD shift registers.

Abstract: A coded electric signal generating keyboard for a single element typewriter is disclosed which has a keylever signal storing function and includes an interlock mechanism for permitting only one interposer at a time to be moved out of its normal position. Thus after depression of a particular key another key is prevented from being depressed until the interposer moved to an operative position is restored to the normal position during an initial part of a printing cycle initiated in response to depression of the particular key. It further includes an arresting mechanism operable to arrest another subsequently released interposer to an intermediate stored position during the remaining part of the printing cycle whereby another printing cycle may be initiated at the end of such printing cycle.