Patents by Inventor Michihito Ueda

Michihito Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9939314
    Abstract: The present invention provides a shock recording device includes: an electric power source; a vibration energy harvester including a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, the first transistor further including a stacked structure of a ferroelectric layer and a semiconductor layer; and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is electrically connected to the first electrode. The second drain electrode is electrically connected to the electric power source. The second source electrode is electrically connected to the first gate electrode. The first source electrode is electrically connected to the second electrode.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: April 10, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukihiro Kaneko, Michihito Ueda, Yu Nishitani
  • Patent number: 9818057
    Abstract: In a neural network circuit element, a neuron circuit includes a waveform generating circuit for generating an analog pulse voltage, and a switching pulse voltage which is input as a first input signal to another neural network circuit element; a synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to a third terminal of a variable resistance element of the synapse circuit, for a permissible input period, in the first input signal from another neural network circuit element; and the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between a first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: November 14, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yu Nishitani, Yukihiro Kaneko, Michihito Ueda
  • Patent number: 9792547
    Abstract: A neural network circuit includes an error calculating circuit that generates an error voltage signal having a magnitude in accordance with a time difference between an output signal and a teaching signal corresponding to the output signal. A weight change pulse voltage signal is input to a synapse circuit of a neural network circuit element including a neuron circuit that output the weight change pulse voltage signal, and a switching pulse voltage signal is input to a synapse circuit of a neural network circuit element other than the neural network circuit element including the neuron circuit that output the switching pulse voltage signal. The neural network circuit element changes the amplitude of the weight change pulse voltage signal on the basis of the error voltage signal generated by the error calculating circuit.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: October 17, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yu Nishitani, Michihito Ueda, Yukihiro Kaneko
  • Patent number: 9563403
    Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: February 7, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Michihito Ueda, Yu Nishitani, Yukihiro Kaneko, Ayumu Tsujimura
  • Publication number: 20160341613
    Abstract: The present invention provides a shock recording device, comprising: a vibration energy harvester comprising a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; and a ferroelectric transistor comprising a gate electrode, a source electrode, and a drain electrode, the ferroelectric transistor further comprising a stacked structure of a ferroelectric layer and a semiconductor layer. The gate electrode is electrically connected to the first electrode. The source electrode is electrically connected to the second electrode. This shock recording device does not need a power source used to record a shock.
    Type: Application
    Filed: August 5, 2016
    Publication date: November 24, 2016
    Inventors: Michihito UEDA, Yukihiro KANEKO, Yu NISHITANI, Atsushi OMOTE
  • Patent number: 9500547
    Abstract: The present invention provides a shock recording device, comprising: a vibration energy harvester comprising a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; and a ferroelectric transistor comprising a gate electrode, a source electrode, and a drain electrode, the ferroelectric transistor further comprising a stacked structure of a ferroelectric layer and a semiconductor layer. The gate electrode is electrically connected to the first electrode. The source electrode is electrically connected to the second electrode. This shock recording device does not need a power source used to record a shock.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 22, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Michihito Ueda, Yukihiro Kaneko, Yu Nishitani, Atsushi Omote
  • Patent number: 9435704
    Abstract: The present invention provides a shock recording device, comprising: a vibration energy harvester comprising a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; and a ferroelectric transistor comprising a gate electrode, a source electrode, and a drain electrode, the ferroelectric transistor further comprising a stacked structure of a ferroelectric layer and a semiconductor layer. The gate electrode is electrically connected to the first electrode. The source electrode is electrically connected to the second electrode. This shock recording device does not need a power source used to record a shock.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Michihito Ueda, Yukihiro Kaneko, Yu Nishitani, Atsushi Omote
  • Patent number: 9391260
    Abstract: Provided is a novel actuator and a method for driving the same. The present invention is an actuator comprising a first laminate comprising a first (Bi, Na, Ba) TiO3 layer between first and second electrode layers, a second laminate comprising a second (Bi, Na, Ba) TiO3 layer between third and fourth electrode layers, and a tilt part provided between the first and second laminates. Both of the first and second (Bi, Na, Ba) TiO3 layers are preferentially oriented in a [011] crystalline axis direction. Voltages V5a, V9a, V5b, and V9b which satisfy Requirement A: V5a>V9a and V5b<V9b or Requirement B: V5a<V9a and V5b>V9b are applied to the first-fourth electrode layers so as to tilt the tilt part. One of the first edge and the second edge is moved in the [011] crystalline axis direction and the other is moved in the reverse direction thereof.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: July 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Michihito Ueda, Takakiyo Harigai, Yoshiaki Tanaka, Hideaki Adachi, Eiji Fujii
  • Publication number: 20150269483
    Abstract: A neural network circuit includes an error calculating circuit that generates an error voltage signal having a magnitude in accordance with a time difference between an output signal and a teaching signal corresponding to the output signal. A weight change pulse voltage signal is input to a synapse circuit of a neural network circuit element including a neuron circuit that output the weight change pulse voltage signal, and a switching pulse voltage signal is input to a synapse circuit of a neural network circuit element other than the neural network circuit element including the neuron circuit that output the switching pulse voltage signal. The neural network circuit element changes the amplitude of the weight change pulse voltage signal on the basis of the error voltage signal generated by the error calculating circuit.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 24, 2015
    Inventors: YU NISHITANI, MICHIHITO UEDA, YUKIHIRO KANEKO
  • Publication number: 20150241464
    Abstract: The present invention provides a shock recording device consisting of: an electric power source; a vibration energy harvester comprising a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, the first transistor further comprising a stacked structure of a ferroelectric layer and a semiconductor layer; and a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is electrically connected to the first electrode. The second drain electrode is electrically connected to the electric power source. The second source electrode is electrically connected to the first gate electrode. The first source electrode is electrically connected to the second electrode.
    Type: Application
    Filed: February 16, 2015
    Publication date: August 27, 2015
    Inventors: YUKIHIRO KANEKO, MICHIHITO UEDA, YU NISHITANI
  • Publication number: 20150241289
    Abstract: The present invention provides a shock recording device, comprising: a vibration energy harvester comprising a first electrode and a second electrode, the vibration energy harvester converting an energy of a shock applied thereto into a potential difference between the first electrode and the second electrode; and a ferroelectric transistor comprising a gate electrode, a source electrode, and a drain electrode, the ferroelectric transistor further comprising a stacked structure of a ferroelectric layer and a semiconductor layer. The gate electrode is electrically connected to the first electrode. The source electrode is electrically connected to the second electrode. This shock recording device does not need a power source used to record a shock.
    Type: Application
    Filed: February 16, 2015
    Publication date: August 27, 2015
    Inventors: MICHIHITO UEDA, YUKIHIRO KANEKO, YU NISHITANI, ATSUSHI OMOTE
  • Publication number: 20150178619
    Abstract: In a neural network circuit element, a neuron circuit includes a waveform generating circuit for generating an analog pulse voltage, and a switching pulse voltage which is input as a first input signal to another neural network circuit element; a synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to a third terminal of a variable resistance element of the synapse circuit, for a permissible input period, in the first input signal from another neural network circuit element; and the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between a first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period.
    Type: Application
    Filed: January 30, 2015
    Publication date: June 25, 2015
    Inventors: Yu NISHITANI, Yukihiro KANEKO, Michihito UEDA
  • Publication number: 20150100614
    Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: MICHIHITO UEDA, YU NISHITANI, YUKIHIRO KANEKO, AYUMU TSUJIMURA
  • Patent number: 8965821
    Abstract: A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yu Nishitani, Yukihiro Kaneko, Michihito Ueda
  • Patent number: 8775346
    Abstract: A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a bipolar sawtooth pulse voltage, and a first input signal has a bipolar sawtooth pulse waveform. For a period during which the first input signal is permitted to be input to a first electrode of a variable resistance element, the bipolar sawtooth pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element is input to a control electrode of the variable resistance element. The resistance value of the variable resistance element changes due to an electric potential difference between the first electrode and the control electrode, the electric potential difference being generated depending on an input timing difference between a voltage applied to the first electrode and the voltage applied to the control electrode.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Yu Nishitani, Yukihiro Kaneko, Michihito Ueda
  • Patent number: 8773212
    Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, which comprise a resistance and a capacitance. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitance. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Yu Nishitani, Yukihiro Kaneko, Michihito Ueda
  • Patent number: 8773213
    Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, each of which comprises a resistance and a capacitor. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitor. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Yu Nishitani, Yukihiro Kaneko, Michihito Ueda
  • Publication number: 20130320806
    Abstract: Provided is a novel actuator and a method for driving the same. The present invention is an actuator comprising a first laminate comprising a first (Bi, Na, Ba) TiO3 layer between first and second electrode layers, a second laminate comprising a second (Bi, Na, Ba) TiO3 layer between third and fourth electrode layers, and a tilt part provided between the first and second laminates. Both of the first and second (Bi, Na, Ba) TiO3 layers are preferentially oriented in a [011] crystalline axis direction. Voltages V5a, V9a, V5b, and V9b which satisfy Requirement A: V5a>V9a and V5b<V9b or Requirement B: V5a<V9a and V5b>V9b are applied to the first-fourth electrode layers so as to tilt the tilt part. One of the first edge and the second edge is moved in the [011] crystalline axis direction and the other is moved in the reverse direction thereof.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 5, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Michihito UEDA, Takakiyo HARIGAI, Yoshiaki TANAKA, Hideaki ADACHI, Eiji FUJII
  • Publication number: 20130311414
    Abstract: A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Yu Nishitani, Yukihiro KANEKO, Michihito UEDA
  • Publication number: 20130311415
    Abstract: A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a bipolar sawtooth pulse voltage, and a first input signal has a bipolar sawtooth pulse waveform. For a period during which the first input signal is permitted to be input to a first electrode of a variable resistance element, the bipolar sawtooth pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element is input to a control electrode of the variable resistance element. The resistance value of the variable resistance element changes due to an electric potential difference between the first electrode and the control electrode, the electric potential difference being generated depending on an input timing difference between a voltage applied to the first electrode and the voltage applied to the control electrode.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Yu NISHITANI, Yukihiro KANEKO, Michihito UEDA