Abstract: A temperature sensor includes first and second lower electrodes, a ferroelectric layer having polarization, a semiconductor layer; and first to third upper electrodes. The second upper electrode is interposed between the first upper electrode and the third upper electrode in a plan view. The semiconductor layer includes a first channel disposed between the first upper electrode and the second upper electrode, and a second channel disposed between the second upper electrode and the third upper electrode. The ferroelectric layer includes a first ferroelectric part disposed below the first channel and a second ferroelectric part disposed below the second channel. A polarization direction of the first ferroelectric part is opposite to a polarization direction of the second first ferroelectric part. The temperature is calculated based on the output voltage from the second upper electrode and the voltage applied to the first upper electrode.

Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, each of which comprises a resistance and a capacitor. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitor. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.

Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, which comprise a resistance and a capacitance. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitance. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.

Abstract: In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2<Vs, and V2<Vd, are applied to write a second resistance value, and (3) the voltages V1, V2, Vs, and Vd, which satisfy V1<Vs, V1<Vd, V2<Vs, and V2<Vd, are applied to write a third resistance value.

Abstract: The purpose of the present invention is to provide a method for driving an actuator in which unnecessary deformation is suppressed. The present invention provides a method for driving an actuator, comprising the following steps (a) and (b): a step (a) of preparing the actuator, wherein the actuator comprises a first electrode, a piezoelectric layer composed of (Bi,Na,Ba)TiO3, and a second electrode, the piezoelectric layer is interposed between the first electrode and the second electrode, +X direction, +Y direction, and +Z direction denote [100] direction, [01-1] direction, and [011] direction, respectively, and the piezoelectric layer is preferentially oriented along the +Z direction; and a step (b) of applying a potential difference between the first electrode and the second electrode to drive the actuator.

Abstract: The purpose of the present invention is to provide a method for driving an actuator in which unnecessary deformation is suppressed. The present invention provides a method for driving an actuator, comprising the following steps (a) and (b): a step (a) of preparing the actuator, wherein the actuator comprises a first electrode, a piezoelectric layer composed of (Bi,Na,Ba)TiO3, and a second electrode, the piezoelectric layer is interposed between the first electrode and the second electrode, +X direction, +Y direction, and +Z direction denote [100] direction, [01-1] direction, and [011] direction, respectively, and the piezoelectric layer is preferentially oriented along the +Z direction; and a step (b) of applying a potential difference between the first electrode and the second electrode to drive the actuator.

Abstract: Provided is a relatively easy-to-fabricate piezoelectric power generating element capable of generating a large amount of electric power while comprising a bridge-type vibration beam that is resistant to damage from external vibration. This element comprises a support member, a strip-shaped vibration beam, a piezoelectric layer, and electrodes. The first and second ends of the vibration beam are fixed to the support member. The piezoelectric layer and the electrodes are provided on the surface of the vibration beam. The vibration beam extends in a plane when it is not vibrating. The vibration beam has a first portion that extends from the first end fixed to the support member, a second portion that extends from the second end fixed to the support member, and a third portion that connects the end of the first portion opposite to the first end and the end of the second portion opposite to the second end.

Abstract: In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2<Vs, and V2<Vd, are applied to write a second resistance value, and (3) the voltages V1, V2, Vs, and Vd, which satisfy V1<Vs, V1<Vd, V2<Vs, and V2<Vd, are applied to write a third resistance value.

Abstract: A temperature sensor includes first and second lower electrodes, a ferroelectric layer having polarization, a semiconductor layer; and first to third upper electrodes. The second upper electrode is interposed between the first upper electrode and the third upper electrode in a plan view. The semiconductor layer includes a first channel disposed between the first upper electrode and the second upper electrode, and a second channel disposed between the second upper electrode and the third upper electrode. The ferroelectric layer includes a first ferroelectric part disposed below the first channel and a second ferroelectric part disposed below the second channel. A polarization direction of the first ferroelectric part is opposite to a polarization direction of the second first ferroelectric part. The temperature is calculated based on the output voltage from the second upper electrode and the voltage applied to the first upper electrode.

Abstract: Provided is a relatively easy-to-fabricate piezoelectric power generating element capable of generating a large amount of electric power while comprising a bridge-type vibration beam that is resistant to damage from external vibration. This element comprises a support member, a strip-shaped vibration beam, a piezoelectric layer, and electrodes. The first and second ends of the vibration beam are fixed to the support member. The piezoelectric layer and the electrodes are provided on the surface of the vibration beam. The vibration beam extends in a plane when it is not vibrating. The vibration beam has a first portion that extends from the first end fixed to the support member, a second portion that extends from the second end fixed to the support member, and a third portion that connects the end of the first portion opposite to the first end and the end of the second portion opposite to the second end.

Abstract: A stochastic processor of the present invention includes a fluctuation generator configured to output an analog quantity having a fluctuation, a fluctuation difference calculation means configured to output fluctuation difference data with an output of the fluctuation generator added to analog difference between two data, a thresholding unit configured to perform thresholding on an output of the fluctuation difference calculation means to thereby generate a pulse, and a pulse detection means configured to detect the pulse output from the thresholding unit.

Abstract: A stochastic pulse generator (1) of this invention includes a variable signal generator (61) operative to generate a variable signal (VC) which varies randomly, and a comparator (3) operative to output a binary signal (Vout) of High or Low depending on which of one input signal and another input signal is larger or smaller than the other, wherein when the variable signal (VC) is inputted, as the one input signal, to the comparator (3) from the variable signal generator (61), the comparator (3) stochastically outputs pulses, the number of which corresponds to a magnitude of the another input signal.

Abstract: An object of the present invention is to provide a method of forming fine particles on a substrate in which reoxidization of reduced fine particles is suppressed. Reduced fine particles (FeO fine particles) are formed by embedding metal oxide fine particles (Fe2O3 fine particles) fixed on a p type silicon semiconductor substrate into a silicon oxidized film, and carrying out a heat treatment in a reducing gas atmosphere. Presence of the silicon oxidized film enables suppression of reoxidization of the reduced fine particles (FeO fine particles) due to exposure to the ambient air.

Abstract: A stochastic processor and a stochastic computer comprises a fluctuation generator configured to generate and output analog quantity having fluctuation comprised of chaos of tent mapping, a mixer configured to output a fluctuation superposed signal with the analog quantity output from the fluctuation generator superposed on an input signal represented by analog quantity and a thresholding unit configured to perform thresholding on the fluctuation superposed signal output from the mixer to generate and output a pulse.

Abstract: A stochastic pulse generator (1) of this invention includes a variable signal generator (61) operative to generate a variable signal (Vc) which varies randomly, and a comparator (3) operative to output a binary signal (Vout) of High or Low depending on which of one input signal and another input signal is larger or smaller than the other, wherein when the variable signal (Vc) is inputted, as the one input signal, to the comparator (3) from the variable signal generator (61), the comparator (3) stochastically outputs pulses, the number of which corresponds to a magnitude of the another input signal.

Abstract: A voltage generating circuit comprising a capacitor (4), a ferroelectric capacitor (6) serially connected to the capacitor (4), an output terminal (11), a capacitor (10) which grounds the output terminal (11), a supply voltage supplying terminal (13), a switch (1) which connects the supply voltage supplying terminal (13) and the connecting node (N1) of the two capacitors (4, 6), and a switch (9) which connects the connecting node (N1) and output terminal (11); wherein during a first period, with the two switches (1) and (9) placed in the OFF state, a terminal (3) is grounded and a terminal (7) is provided with a supply voltage; wherein during a second period, the terminal (3) is provided with the supply voltage and the switch (9) is placed in the ON state; wherein during a third period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is grounded; wherein during a fourth period, the terminal (7) is provided with the supply voltage; and wherein thereafte

Abstract: An object of the present invention is to provide a method of forming fine particles on a substrate in which reoxidization of reduced fine particles is suppressed. Reduced fine particles (FeO fine particles) are formed by embedding metal oxide fine particles (Fe2O3 fine particles) fixed on a p type silicon semiconductor substrate into a silicon oxidized film, and carrying out a heat treatment in a reducing gas atmosphere. Presence of the silicon oxidized film enables suppression of reoxidization of the reduced fine particles (FeO fine particles) due to exposure to the ambient air.

Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

Abstract: In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

Abstract: A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.