Patents by Inventor Michikazu Matsumoto
Michikazu Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7851891Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.Type: GrantFiled: April 16, 2009Date of Patent: December 14, 2010Assignee: Panasonic CorporationInventors: Naohisa Sengoku, Michikazu Matsumoto
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Patent number: 7800181Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.Type: GrantFiled: October 18, 2006Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
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Patent number: 7585767Abstract: A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.Type: GrantFiled: February 21, 2006Date of Patent: September 8, 2009Assignee: Panasonic CorporationInventors: Yasutoshi Okuno, Michikazu Matsumoto
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Publication number: 20090206454Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.Type: ApplicationFiled: April 16, 2009Publication date: August 20, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Naohisa SENGOKU, Michikazu Matsumoto
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Patent number: 7253436Abstract: A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.Type: GrantFiled: July 22, 2004Date of Patent: August 7, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michikazu Matsumoto, Yasutoshi Okuno, Katsuyoshi Joukyu, Tetsuya Matsutani
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Publication number: 20070158760Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.Type: ApplicationFiled: March 16, 2007Publication date: July 12, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yasutoshi Okuno, Michikazu Matsumoto
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Publication number: 20070093047Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.Type: ApplicationFiled: October 18, 2006Publication date: April 26, 2007Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
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Patent number: 7202147Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.Type: GrantFiled: November 29, 2005Date of Patent: April 10, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasutoshi Okuno, Michikazu Matsumoto
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Patent number: 7126174Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: November 24, 2004Date of Patent: October 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20060187719Abstract: In ID generation for a semiconductor package or a semiconductor integrated circuit chip, a topographic characteristic to be utilized as specific information is selected from at least one topographic characteristic that the semiconductor package or the semiconductor integrated circuit has. Then, the selected topographic characteristic is measured as the specific information and an ID for identification is generated for the semiconductor package or the semiconductor integrated circuit chip based on the measured specific information.Type: ApplicationFiled: October 3, 2005Publication date: August 24, 2006Inventors: Michikazu Matsumoto, Yasutoshi Okuno, Kazuyoshi Tsukamoto, Toshiki Yabu
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Publication number: 20060189087Abstract: A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.Type: ApplicationFiled: February 21, 2006Publication date: August 24, 2006Inventors: Yasutoshi Okuno, Michikazu Matsumoto
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Publication number: 20060138562Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.Type: ApplicationFiled: November 29, 2005Publication date: June 29, 2006Inventors: Yasutoshi Okuno, Michikazu Matsumoto
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Publication number: 20050263833Abstract: A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.Type: ApplicationFiled: August 3, 2005Publication date: December 1, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Naohisa Sengoku, Michikazu Matsumoto
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Patent number: 6967409Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: June 5, 2003Date of Patent: November 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6946305Abstract: A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.Type: GrantFiled: October 15, 2003Date of Patent: September 20, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naohisa Sengoku, Michikazu Matsumoto
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Publication number: 20050156220Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: March 17, 2005Publication date: July 21, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20050093089Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: November 24, 2004Publication date: May 5, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6879043Abstract: The electrode structure of this invention includes a silicon-containing film containing silicon as a principal constituent; a barrier metal layer of titanium nitride rich in titanium as compared with a stoichiometric ratio formed on the silicon-containing film; and a metal film with a high melting point formed on the barrier metal layer.Type: GrantFiled: August 7, 2001Date of Patent: April 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michikazu Matsumoto, Naohisa Sengoku
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Publication number: 20050017746Abstract: A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.Type: ApplicationFiled: July 22, 2004Publication date: January 27, 2005Inventors: Michikazu Matsumoto, Yasutoshi Okuno, Katsuyoshi Joukyu, Tetsuya Matsutani
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Patent number: 6847119Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: June 5, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto