Abstract: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes (1d) are formed in the centers of the signal coils (1b) of the silicon substrate (1a). Signal coils (2c) connected to solder balls (5) by way of through-conductors (2d) are formed on the interposer (2). Magnetic pins (3) that are composed of a magnetic material are inserted in the centers of the signal coils (1b and 2c).

Abstract: The semiconductor device testing apparatus has a testing LSI; a power supply unit; and an intermediate substrate. The testing LSI has a dielectric material layer facing a tested semiconductor device; an electrode disposed in a position corresponding to a position of an external terminal electrode of the tested device on a surface of the dielectric layer facing the tested device; and a first penetrating electrode that passes completely through the dielectric layer, is connected to the electrode, and is used for exchanging signals with the exterior. The power supply unit has mutually independent elastic probe pins that are disposed in positions corresponding to power electrodes of the tested device, and that are provided with a metal protrusion at the distal ends thereof; a substrate on which a first wiring layer is formed and is electrically connected to the probe pins; and a second penetrating electrode that passes through the substrate.

Abstract: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes (1d) are formed in the centers of the signal coils (1b) of the silicon substrate (1a). Signal coils (2c) connected to solder balls (5) by way of through-conductors (2d) are formed on the interposer (2). Magnetic pins (3) that are composed of a magnetic material are inserted in the centers of the signal coils (1b and 2c).

Abstract: A conventional inspection probe has posed such problems that, when a pitch is as fine as up to 40 ?m, a positional accuracy is difficult to ensure depending on constituting materials and a production method, pin breaking occurs when fine-diameter pins contact, a good contact cannot be obtained due to an insufficient contact, an durability is insufficient. An inspection probe having a probe structure comprising an elastic probe pin, a wiring layer carrying substrate, a backup plate to install a substrate thereon, an inspection substrate and a flexible substrate, characterized in that a good-contact material layer according to the electrode material of a semiconductor device is formed at the tip end of a probe pin and a wiring layer has a structure formed of a low-resistance metal layer, with the good-contact material layer being separated from the low-resistance metal layer. Such a structure can provide very high contact reliability and mechanical durability at a pitch as very fine as up to 40 ?m.

Abstract: The semiconductor device testing apparatus according to the present invention has a testing LSI; a power supply unit; and an intermediate substrate provided so that there is a connection between the testing LSI, and the power supply unit and tester. The testing LSI has a testing circuit and a waveform shaping circuit; a dielectric material layer disposed so as to face a tested semiconductor device; an electrode disposed in a position that corresponds to a position of an external terminal electrode of the tested semiconductor device on a surface of the dielectric material layer facing the tested semiconductor device; and a first penetrating electrode that passes completely through the dielectric material layer, is connected to the electrode, and is used for exchanging signals with the exterior.

Abstract: An inspection probe comprises resilient probe pins having electric contacts disposed in positions corresponding to electrodes of an external terminal of a semiconductor device, a base substrate including pitch-expansion wiring layers of the probe pins, and a backup substrate, the base substrate, and a flexible substrate, wherein at least one precious metal layer is disposed at the tip of the probe pins on the side having the electric contact for contacting the electrodes of the semiconductor device to be inspected, at least one metal layer is disposed on the probe pins and the pitch-expansion wiring layers, the precious metal layer and the metal layer are composed of the same material or composed of different materials, and a roughness pattern comprising fine marks is provided on the surfaces of the probe pins on the side having the electric contacts for contacting the electrodes of the semiconductor device to be inspected.

Abstract: A conventional inspection probe has posed such problems that, when a pitch is as fine as up to 40 ?m, a positional accuracy is difficult to ensure depending on constituting materials and a production method, pin breaking occurs when fine-diameter pins contact, a good contact cannot be obtained due to an insufficient contact, an durability is insufficient. An inspection probe having a probe structure comprising an elastic probe pin, a wiring layer carrying substrate, a backup plate to install a substrate thereon, an inspection substrate and a flexible substrate, characterized in that a good-contact material layer according to the electrode material of a semiconductor device is formed at the tip end of a probe pin and a wiring layer has a structure formed of a low-resistance metal layer, with the good-contact material layer being separated from the low-resistance metal layer. Such a structure can provide very high contact reliability and mechanical durability at a pitch as very fine as up to 40 ?m.

Abstract: An inspection probe comprises resilient probe pins having electric contacts disposed in positions corresponding to electrodes of an external terminal of a semiconductor device, a base substrate including pitch-expansion wiring layers of the probe pins, and a backup substrate, the base substrate, and a flexible substrate, wherein at least one precious metal layer is disposed at the tip of the probe pins on the side having the electric contact for contacting the electrodes of the semiconductor device to be inspected, at least one metal layer is disposed on the probe pins and the pitch-expansion wiring layers, the precious metal layer and the metal layer are composed of the same material or composed of different materials, and a roughness pattern comprising fine marks is provided on the surfaces of the probe pins on the side having the electric contacts for contacting the electrodes of the semiconductor device to be inspected.

Abstract: Semiconductor device inspection apparatus suitable for inspecting narrow-pitched semiconductor devices and an inspection method. The apparatus has a wafer stage, a base table, an X stage, a Y stage, an elevation unit mounted on the Y stage and elevates the wafer stage up and down, a rotary unit which turns the wafer stage, a vibration elimination table which reduces vibration of the base table, a probe card having plural probe needles which electrically contact plural electrodes when the wafer stage moves upward, and a probe card holder where the probe card is to be placed. The heights of needles of the probe card are detected by a laser displacement meter. Images of a wafer and the needles are sensed by a camera. Based on image information, positions of the wafer and probe card are computed and the X stage, Y stage and elevation unit are controlled.

Abstract: Disclosed are a semiconductor device inspection apparatus suitable for inspecting narrow-pitched semiconductor devices and an inspection method which uses the apparatus. The apparatus has a wafer stage, a base table, an X stage, a Y stage, an elevation unit which is mounted on the Y stage and elevates the wafer stage up and down, a rotary unit which turns the wafer stage, a vibration elimination table which reduces vibration of the base table, a probe card having plural probe needles which electrically contact plural electrodes when the wafer stage moves upward, and a probe card holder where the probe card is to be placed. The heights of needles of the probe card are detected by a laser displacement meter. Images of a wafer and the needles are sensed by a camera. Based on image information, positions of the wafer and probe card are computed and the X stage, Y stage and elevation unit are controlled.

Abstract: A probe is provided so as to obtain an electrical contact between a semiconductor device having a plurality of first electrodes as external terminals and an inspection substrate having a plurality of second electrodes so as to inspect the semiconductor device. A first substrate has through holes formed at positions corresponding to the first electrodes. Probe pins are fixed in the through holes. A second substrate has a rewiring layer for extending a pitch of the first electrodes and penetration electrodes for drawing out the first electrodes to a back surface. A contact is disposed between the penetration electrodes and the second electrodes and has conductivity and elasticity only in a vertical direction.

Abstract: A test probe has a sheet body including an insulating sheet and a wiring sheet formed on the bottom surface of the insulating sheet. The insulating sheet mounts on the top surface a plurality of top electrodes arranged with a small pitch, whereas the wiring sheet mounts on the bottom surface a plurality of bottom electrodes connected to the top electrodes through via-holes in the insulating sheet and interconnect layers in the wiring sheet. A smaller pitch of the top electrodes is suited for a bare chip LSI, whereas a larger pitch of the bottom electrodes reduces the cost for a test board.

Abstract: A semiconductor device testing apparatus that has a laminate structure composed of a contact sheet having a first opening, an elastic sheet having a second opening and a base plate having a third opening. A supply voltage is applied to an external terminal located on a peripheral portion of the contact sheet. A probe of a probe portion is contacted to a signal electrode of a semiconductor device through the third, second and first openings.

Abstract: A probe is provided so as to obtain an electrical contact between a semiconductor device having a plurality of first electrodes as external terminals and an inspection substrate having a plurality of second electrodes so as to inspect the semiconductor device. A first substrate has through holes formed at positions corresponding to the first electrodes. Probe pins are fixed in the through holes. A second substrate has a rewiring layer for extending a pitch of the first electrodes and penetration electrodes for drawing out the first electrodes to a back surface. A contact is disposed between the penetration electrodes and the second electrodes and has conductivity and elasticity only in a vertical direction.

Abstract: There is provided a semiconductor device tester including (a) a tester substrate having the same structure as a structure of a substrate as a product except that a semiconductor device is not mounted on the tester substrate, (b) an electrically conductive sheet covering therewith a first area in which the semiconductor device is to be mounted on the tester substrate, the electrically conductive sheet being electrically insulating in a certain direction, and (c) a holder supporting a semiconductor device to be tested therewith, and compressing the semiconductor device onto the electrically conductive sheet to thereby electrically connect an externally projecting terminal of the semiconductor device to a connection terminal mounted on the tester substrate in the first area.

Abstract: The present invention provides a bare chip carrier comprising: a carrier body having a base portion on which a bare chip is mounted and also having at least one cap holder ; and a carrier cap having a pressing member for pressing the bare chip toward the base portion of the body, and the carrier cap being separated from the carrier body, wherein the at least one cap holder has at least a holder engagement portion which is to be engaged with a cap engagement portion of the carrier cap, so that the carrier cap separated from the carrier body is held by the at least one cap holder, whereby the bare chip is mounted by only a single operation of dropping the carrier cap onto the carrier body for realizing the automation.

Abstract: A test carrier according to the present invention can materialize stable contact between electrode bumps of a semiconductor device and a contact sheet no matter where the electrode bumps are. The test carrier comprises a contact sheet 4 disposed on a carrier base 1 and having bumps 50 in contact with and connected to electrode pads on the surface of the semiconductor device and external electrodes 48 for testing, a pressing member 6 for applying predetermined contact pressure between the electrode pads and the bumps 50, and a securing member 70 for securing the contact sheet on the carrier base. The center of thermal expansion of the contact sheet secured by the securing member 70 is offset from all the bumps 50. Further, the securing member 70 secures the carrier base and the contact sheet at two or more securing points, and the center of a figure formed by linking the securing points is offset from the bumps 50.

Abstract: A surface elastic wave device is provided in which an influence of the stress based on a difference of the coefficients of thermal expansion between the surface elastic wave chip and a wiring substrate is reduced and a connection defective due to heat is prevented. When quartz is used for a surface elastic wave substrate (K1) and aluminum is used for the wiring substrate (52), the surface elastic wave device is characterized in that bumps are arranged within a definite area (B1) in aluminum pads (input electrode pad (4), output electrode pad (5), and ground electrode pads (G1 to G8)) placed on a functional surface of the surface elastic wave chip (1). According to the present invention, an area in which the bumps are formed, a film thickness of an aluminum pad (Al film thickness), the chip size of the surface elastic wave chip (1), and the number of the bumps are defined to a surface elastic wave substrate of quartz or LiTaO3.

Abstract: A probe structure according to the invention includes a base substrate 7, a plurality of probe pins 3 provided at predetermined respective positions on a top side of the base substrate, a plurality of through electrodes 5 respectively corresponding to a plurality of electrodes K1 of a testing board K, and rewiring layers 4 for electrically interconnecting each of the probe pins 3 and each of the through electrodes 5 individually on the top side of the base substrate, in which the probe pins 3 are each composed of a silicon-made core and a conductive film 32 formed thereon and the through electrodes 5 each pass through the base substrate 7 from one side to the other thereof and have a pitch thereof set larger than a pitch of the probe pins.

Abstract: There is provided a semiconductor device testing apparatus that can perform a measurement of an electrical characteristic of a semiconductor device that has many electrodes and operates at high frequency. The semiconductor device testing apparatus comprises: a contact sheet (105) having supply voltage electrodes (107c, 107b) of bump structure on a thin insulator sheet (105a), which contact with a source electrode (100c) and a ground electrode (100b) of a semiconductor device (100), and a first opening (113) located at a position facing a signal (100a) of the semiconductor device (100).