Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.

Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlaver dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlayer dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: A method of fabricating a semiconductor device comprises the following steps (a) to (f): (a) a step of forming a the contact hole in an interlayer dielectric formed on a semiconductor substrate including an electronic element; (b) a degassing step for removing gaseous components included within the interlayer dielectric, by thermal processing under a reduced pressure at a substrate temperature of 300° C. to 550° C.; (c) a step of forming a barrier layer on the interlayer dielectric and the contact hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer on the barrier layer, at a temperature of no more than 200° C., including aluminum or an alloy in which aluminum is the main component; and (f) a step is of forming a second aluminum layer on the first aluminum layer, at a temperature of at least 300° C., including aluminum or an alloy in which aluminum is the main component.

Abstract: A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlayer dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: A semiconductor device is manufactured by a method including the steps of forming a through hole in an interlayer dielectric layer (silicon oxide layer, BPSG layer, etc.) formed on a semiconductor substrate having a device element. A barrier layer is formed on surfaces of the interlayer dielectric layer and the through hole. A wiring layer is formed on the barrier layer. The barrier layer is formed by a method including the following steps. A titanium layer that forms at least a part of the barrier layer is formed. A heat treatment is conducted in a nitrogen atmosphere to form a titanium nitride layer at least on a surface of the titanium layer. The titanium nitride layer is contacted with oxygen in an atmosphere including oxygen. A heat treatment is conducted in a nitrogen atmosphere to form titanium oxide layers and to densify the titanium nitride layer.

Abstract: A method of fabricating a semiconductor device comprises the following steps (a) to (f): (a) a step of forming a the contact hole in an interlayer dielectric formed on a semiconductor substrate including an electronic element; (b) a degassing step for removing gaseous components included within the interlayer dielectric, by thermal processing under a reduced pressure at a substrate temperature of 300° C. to 550° C.; (c) a step of forming a barrier layer on the interlayer dielectric and the contact hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer on the barrier layer, at a temperature of no more than 200° C., including aluminum or an alloy in which aluminum is the main component; and (f) a step is of forming a second aluminum layer on the first aluminum layer, at a temperature of at least 300° C., including aluminum or an alloy in which aluminum is the main component.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: A semiconductor device comprising a semiconductor substrate including an electronic element such as a MOSFET, interlayer dielectric (silicon oxide layer or BPSG layer) formed on the semiconductor substrate, a through-hole formed in the interlayer dielectric, a barrier layer formed on a surface of the interlayer dielectric and on a surface of the through-hole, and a metal wiring layer formed on the barrier layer. The metal wiring layer contains aluminum as its major component and 0.1 wt % to 3 wt % of beryllium. An aluminum alloy can be embedded in the through-hole without creation of any void or breaking of wire, and the semiconductor device is highly resistant to electro-migration.

Abstract: A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element comprises at least the following steps (a) to (c): (a) a step of forming a first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method; (b) a step of forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; and (c) a step of annealing at a temperature of 300° C. to 850° C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required for a BPSG film, and it has superior self-flattening characteristics in itself.

Abstract: A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier layer formed on the interlayer dielectric and contact hole, and a wiring layer formed on the barrier layer. In the barrier layer, metal oxide (titanium oxide) are scattered in an island-like configuration. The barrier layer is formed by depositing a layer that is used to form the barrier layer and then introducing oxygen into the layer. The step is achieved by depositing a layer for the barrier layer, exposing the layer in oxygen plasma under reduced pressure, and subjecting the layer to the thermal processing, or, alternatively by depositing a layer for the barrier layer and subjecting the layer to thermal processing in an atmosphere of oxygen. The semiconductor device of the present invention has a barrier layer with excellent barrier properties.

Abstract: A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element includes:forming first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method;forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; andannealing at a temperature of 300.degree. C. to 850.degree. C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required of a BPSG film, and it has superior self-flattening characteristics in itself.