Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300.degree. C. to 550.degree. C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100.degree. C.

Abstract: A semiconductor device composed of: a substrate having a doped semiconductor region, a gate wiring, a lower conductor structure, an insulating layer overlying the lower structure and having at least one through opening extending to the lower conductor structure, and an upper conductor structure connected to the lower conductor structure via the through opening, wherein at least one of the conductor structures is formed of at least one layer of a metal, a metal silicide, a metal nitride, a metal carbide or a conductive oxide film, and a metal plating layer disposed on and adhering to the at least one layer.

Abstract: A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby permitting high speed operation and high density integration to be realized. The formation of the channels by contact self-alignment is accomplished by depositing a P type polysilicon layer on an N well region and an N type polysilicon layer on a P well region. A silicide layer is formed over both the P and N type polysilicon layers to form a polycide.

Abstract: A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby permitting high speed operation and high density integration to be realized. The formation of the channels by contact self-alignment is accomplished by depositing a P type polysilicon layer on an N well region and an N type polysilicon layer on a P well region. A silicide layer is formed over both the P and N type polysilicon layers to form a polycide.

Abstract: A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby permitting high speed operation and high density integration to be realized. The formation of the channels by contact self-alignment is accomplished by depositing a P type polysilicon layer on an N well region and an N type polysilicon layer on a P well region. A silicide layer is formed over both the P and N type polysilicon layers to form a polycide.

Abstract: A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby permitting high speed operation and high density integration to be realized. The formation of the channels by contact self-alignment is accomplished by depositing a P type polysilicon layer on an N well region and an N type polysilicon layer on a P well region. A silicide layer if formed over both the P and N type polysilicon layers to form a polycide.

Abstract: A method for preparing an improved semiconductor device having a transistor and a capacitor or an element isolating region in or on a semiconductor substrate by a self-alignment process is provided. Each of the elements is formed using a previously formed element as a mask so that no additional processes are necessary to align the elements at the desired position. Specifically, a gate electrode is formed first and then a capacitor, element isolating region and contact hole are formed in such a way that the room required for alignment of the gate electrode and the capacitor, the gate electrode and the element isolating region and the gate electrode and the contact hole is reduced. The process is extremely advantageous for miniaturization of the semiconductor device. The device prepared by such a process is also provided.