Patents by Inventor Michio Nakajima
Michio Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120142879Abstract: A composition for film formation according to the present invention includes polymerizable compounds each having at least one polymerizable functional group, and the polymerizable compound includes a partial structure containing an adamantane type cage structure and at least one polymerizable reactive group contributing to polymerization reaction in one molecule thereof. Further, the polymerizable reactive group contains an aromatic ring and at least one ethynyl or vinyl group directly bonded to the aromatic ring as the polymerizable functional group, and the number of carbon atoms derived from the aromatic ring is in the range of 15 to 38% with respect to the number of total carbon atoms of the polymerizable compound.Type: ApplicationFiled: June 25, 2010Publication date: June 7, 2012Applicant: SUMITOMO BAKELITE COMPANY LIMITEDInventors: Michio Nakajima, Hidenori Saito, Takahiro Harada, Mihoko Matsutani, Masahiro Tada, Koji Nakatani
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Patent number: 7661187Abstract: The present invention relates to providing the manufacturing method for a magnetic disk drive that includes the process steps of detecting and processing in a simplified way the defective sectors causing a reading error at low operating environmental temperatures. In one example, defective sectors are detected by read/write testing at high operating environmental temperatures from, for example, 40° C. to 65° C. Reading the data written on the defective sectors makes it obvious that the gain in a high-frequency band is reduced. After test data has been written onto each sector, the filtering coefficient of an FIR element that is set for a data-reading system is changed from the optimum value. The frequency gain is thus reduced. Next, the test data is read and the sectors that have caused a reading error are registered as defectives.Type: GrantFiled: December 5, 2005Date of Patent: February 16, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Masato Taniguchi, Michio Nakajima, Kaoru Umemura
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Patent number: 7457067Abstract: Embodiments of the invention make it possible to conduct stable recording on a magnetic disk, even in case of changes in flying height due to thermal protrusion. In one embodiment, a compensatory recording current value A2 is used when a first section of user data is recorded in the required number of data sectors from the data sector of the starting address for recording the user data to the data sector of an intermediate address. A recording current value A3 smaller than the compensatory recording current value is used when a second section of user data is recorded in the data sectors existing from the data sector of the intermediate address towards the ending address.Type: GrantFiled: September 16, 2005Date of Patent: November 25, 2008Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Yumi Nagano, Michio Nakajima, Toyomi Ohsawa, Masato Taniguchi
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Publication number: 20060126204Abstract: Embodiments of the invention provide the manufacturing method for a magnetic disk drive that includes the process steps of detecting and processing in a simplified way the defective sectors causing a reading error at low operating environmental temperatures. In one embodiment, defective sectors are detected by read/write testing at high operating environmental temperatures from, for example, 40° C. to 65° C. Reading the data written on the defective sectors makes it obvious that the gain in a high-frequency band is reduced. After test data has been written onto each sector, the filtering coefficient of an FIR element that is set for a data-reading system is changed from the optimum value. The frequency gain is thus reduced. Next, the test data is read and the sectors that have caused a reading error are registered as defectives.Type: ApplicationFiled: December 5, 2005Publication date: June 15, 2006Applicant: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Masato Taniguchi, Michio Nakajima, Kaoru Umemura
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Publication number: 20060056091Abstract: Embodiments of the invention make it possible to conduct stable recording on a magnetic disk, even in case of changes in flying height due to thermal protrusion. In one embodiment, a compensatory recording current value A2 is used when a first section of user data is recorded in the required number of data sectors from the data sector of the starting address for recording the user data to the data sector of an intermediate address. A recording current value A3 smaller than the compensatory recording current value is used when a second section of user data is recorded in the data sectors existing from the data sector of the intermediate address towards the ending address.Type: ApplicationFiled: September 16, 2005Publication date: March 16, 2006Applicant: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Yumi Nagano, Michio Nakajima, Toyomi Ohsawa, Masato Taniguchi
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Patent number: 6798598Abstract: A method for controlling write current to a write head during data write on a hard disk drive is disclosed. A direct access storage device includes a rotating storage medium in which data are magnetically written, a write head for writing data in the rotating storage medium, and a write current control circuit for changing write current-value settings to be supplied to the write head according to a predetermined elapsed time from the beginning of a write operation.Type: GrantFiled: March 5, 2002Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: Hiroaki Suzuki, Hideo Asano, Yumi Nagano, Michio Nakajima, Masaomi Ikeda, Masashi Murai
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Patent number: 6794909Abstract: In an output circuit of a semiconductor device, an output buffer circuit includes a P-channel MOS transistor and a resistor connected in series between a line of a power supply potential and an output node. Current driving capability of the output buffer circuit is adjusted by making the P-channel MOS transistor nonconductive when a fuse is not blown, and making P-channel MOS transistor conductive when the fuse is blown. Thus, desired circuit characteristics can be obtained. Further, measures against electrostatic discharge can be taken by providing the resistor between a drain of the P-channel MOS transistor and the output node.Type: GrantFiled: August 21, 2003Date of Patent: September 21, 2004Assignee: Renesas Technology Corp.Inventors: Aki Urakami, Michio Nakajima
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Patent number: 6611571Abstract: An angle demodulator in which an FM modulated wave is converted into an IF signal (SI) in the form of digital so as the signal is supplied to a Hilbert transformer (81) and to an outer product calculation section (82). The Hilbert transformer (81) allows the phase of the IF signal (SI) to shift ninety degrees and supplied it to the outer product calculation section (82). An integrator (84) calculates a phase of a cosine wave of an angular frequency that a frequency control unit (83) designates. A phase converter (85) calculates the cosine wave and an instantaneous value of a signal in which the cosine wave shifts ninety degrees out of phase so as to supply the value to the outer product calculation section (82). The outer product calculation section (82) supplies to the frequency control unit (83) an outer product of a vector including a value of the IF signal and of a signal from the Hilbert transformer (81) and a vector including a value supplied from the phase converter (85).Type: GrantFiled: May 28, 1999Date of Patent: August 26, 2003Assignee: Icom IncorporatedInventor: Michio Nakajima
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Patent number: 6545934Abstract: A semiconductor memory device includes a plurality of regions. Each region includes memory cell arrays, an input/output circuit zone, column decoders, and a row decoder. The input/output circuit zone is placed between the memory cell arrays. The input/output circuit zone inputs or outputs data to or from the memory cell arrays selectively. As a result, high integration is realized with ease.Type: GrantFiled: April 24, 2001Date of Patent: April 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takekazu Yamashita, Michio Nakajima
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Publication number: 20020141094Abstract: A method for controlling write current to a write head during data write on a hard disk drive is disclosed. A direct access storage device includes a rotating storage medium in which data are magnetically written, a write head for writing data in the rotating storage medium, and a write current control circuit for changing write current-value settings to be supplied to the write head according to a predetermined elapsed time from the beginning of a write operation.Type: ApplicationFiled: March 5, 2002Publication date: October 3, 2002Applicant: International Business Machines CorporationInventors: Hiroaki Suzuki, Hideo Asano, Yumi Nagano, Michio Nakajima, Masaomi Ikeda, Masashi Murai
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Patent number: 6423815Abstract: The present invention provides a layer insulating film for multilayer interconnection of semiconductors which is excellent in resistance to heat, resistance to moisture absorption as well as in electric characteristic properties, and a process for producing the film. That is, a layer insulating film for multilayer interconnection of semiconductors which comprises a fluorine-containing polybenzoxazole resin having the structure represented by the formula (6) and obtained by a process which comprises subjecting to heat-dehydrating ring closure a fluorine-containing polyhydroxyamide resin obtained by reacting a dicarboxylic acid diester obtained from one kind of compound selected from the group of compounds represented by the formulas (2) and 2,2′-bis(tri-fluoromethyl)-4,4′-biphenyldicarboxylic acid, with 2,2-bis(3-amino-4-hydroxyphenyl)hexafluoropropane, (in the formula (6), m is an integer of 10-500).Type: GrantFiled: August 29, 2000Date of Patent: July 23, 2002Assignee: Sumitomo Bakelite Company, LimitedInventors: Michio Nakajima, Maki Tokuhiro, Hidenori Saito, Saiko Yoshihashi
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Publication number: 20020034116Abstract: A semiconductor memory device includes a plurality of regions. Each region includes memory cell arrays, an input/output circuit zone, column decoders, and a row decoder. The input/output circuit zone is placed between the memory cell arrays. The input/output circuit zone inputs or outputs data to or from the memory cell arrays selectively. As a result, high integration is realized with ease.Type: ApplicationFiled: April 24, 2001Publication date: March 21, 2002Inventors: Takekazu Yamashita, Michio Nakajima
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Patent number: 6345005Abstract: A read and write control circuit receives (m×n))-bit data output m-bit parallel from a D flip flop, and a q-bit data selection signal such that the output data from the D flip flop is written to memory circuits in units of integral multiples of (x+1) bits in a total of 2q operations, in accordance with a binary value indicated by the data selection signal, where m, n, x and q indicates positive integers (x+1)>m and n>2q, where m, n, x and 1 indicate positive integers and (x+1)>m and n>2q. The data written to the memory circuits is read out in units of integral multiples of (x+1) bits in a total of 2q operations.Type: GrantFiled: December 13, 2000Date of Patent: February 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Aki Urakami, Michio Nakajima
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Publication number: 20010043485Abstract: A read and write control circuit receives (m×n)−bit data output m−bit parallel from a D flip flop, and a q−bit data selection signal such that the output data from the D flip flop is written to memory circuits in units of integral multiples of (x+1) bits in a total of 2q operations, in accordance with a binary value indicated by the data selection signal, where m, n, x and q indicates positive integers (x+1)>m and n>2q, where m, n, x and 1 indicate positive integers and (x+1)>m and n>2q. The data written to the memory circuits is read out in units of integral multiples of (x+1) bits in a total of 2q operations.Type: ApplicationFiled: December 13, 2000Publication date: November 22, 2001Inventors: Aki Urakami, Michio Nakajima
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Patent number: 6204356Abstract: Heat resistant polybenzoxazole resins useful as layer insulation films and protective films for semiconductor, layer insulation films for multilayer circuits, cover coats for flexible copper-clad sheets, solder resist films, liquid crystal-aligned films and the like. These resins have excellent thermal, electrical, physical and mechanical characteristics. Polybenzoxazole precursors are provided, represented by the general formula (A), and are used to obtain polybenzoxazole resins, represented by the general formula (D). In the formulas (A) and (D), n denotes an integer from 2-1000, and X denotes a structure having a formula selected from structures indicated at (B). In the formulas at (B), Y denotes a structure having a formula selected from those indicated at (C), and the hydrogen atom(s) on the benzene ring in these structures are optionally substituted.Type: GrantFiled: September 27, 1999Date of Patent: March 20, 2001Assignee: Sumitomo Bakelite Company LimitedInventors: Hidenori Saito, Michio Nakajima, Tsuyoshi Watanabe, Maki Tokuhiro
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Patent number: 6127694Abstract: Regarding a semiconductor device, a burn-in board can be standardized in each package. An IC (100) includes a VCC terminal (2), a GND terminal (3), input terminals (4a, 4b), and output terminals (5), and it also includes a burn-in board setting terminal (14). Input signals applied to the input terminals (4a, 4b) are transmitted to gates 16a and 16b of switching circuit (15) and processed in a function block (7). Regardless of the signals applied to the input terminals (4a, 4b), simply applying a test signal to the burn-in board setting terminal (14), a specified logic is applied to the function block (7). Only if a pin arrangement of the VCC terminal (2), the GND terminal (3), and the burn-in board setting terminal (14) is standardized and determined, burn-in can be performed indifferent of another pin arrangement of the input terminals (4a, 4b).Type: GrantFiled: June 18, 1993Date of Patent: October 3, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Michio Nakajima
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Patent number: 6114866Abstract: A semiconductor device test board solves a problem with conventional test boards in that test results obtained through a burn-in procedure could be identified only before the test board is taken out of a burn-in oven. Hence, conventional test boards required additional steps for checking the test results after removing the test boards from the burn-in oven. This extra step prevents the efficiency of the test from being improved. One embodiment of the present test board has indicator arms, each rotatably mounted on a pivot on the test board, for indicating, in response to a signal on a signal line, the test result of the semiconductor device associated with it. Each of the indicator arms maintains its rest position when no failure has occurred in the semiconductor device associated with it during the test.Type: GrantFiled: February 4, 1998Date of Patent: September 5, 2000Assignees: Mitsubishi Electric Systems LSI Design Corporation, Mitsubishi Denki KabushikiInventors: Masaaki Matsuo, Tsuyoshi Saitoh, Takekazu Yamashita, Michio Nakajima, Akira Kitaguchi, Hideki Toki
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Patent number: 6043522Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.Type: GrantFiled: April 16, 1998Date of Patent: March 28, 2000Assignees: Mitsubishi Electric System LSI Design Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Michio Nakajima, Makoto Hatakenaka, Akira Kitaguchi, Kiyoyuki Shiroshima, Takekazu Yamashita, Masaaki Matsuo
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Patent number: 6040614Abstract: A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.Type: GrantFiled: March 3, 1998Date of Patent: March 21, 2000Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design CorporationInventors: Akira Kitaguchi, Makoto Hatakenaka, Michio Nakajima, Kaoru Motonami, Kiyoyuki Shiroshima, Takekazu Yamashita
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Patent number: 5999574Abstract: An input analog signal is sampled at a sampling frequency f.sub.s, which is four times a carrier frequency f.sub.c. A demultiplexer 11 outputs supplied data to four systems sequentially, and generates four zero carriers whose frequencies and amplitudes are equal to each other, with only the phases being different. The delay circuits 12 to 15 delay each one of the zero carriers, and supply delayed signals to adaptive filters 16 to 19. Data output from the four adaptive filters 16 to 19 are selected by a multiplexer 22, and the multiplexer 22 outputs the selected signals as a single signal. The difference between a first zero carrier and an output signals of the first adaptive filter 16 is obtained, and tap coefficients of the adaptive filters 16 to 19 are controlled in accordance with an LMS algorithm based on the difference. A signal output by the multiplexer 22 is output as a reproduced carrier.Type: GrantFiled: March 13, 1997Date of Patent: December 7, 1999Assignee: Icom IncorporatedInventors: Weimin Sun, Hirofumi Yamauchi, Michio Nakajima